// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2025.1 (win64) Build 6140274 Thu May 22 00:12:29 MDT 2025
// Date        : Sat Dec 20 18:43:22 2025
// Host        : LAPTOP-L3CRKKNJ running 64-bit major release  (build 9200)
// Command     : write_verilog -force -mode funcsim
//               c:/Vivado_Debug/FNPLL8/FNPLL2.gen/sources_1/bd/FNPLL/ip/FNPLL_delta_sigma_loop_0_0/FNPLL_delta_sigma_loop_0_0_sim_netlist.v
// Design      : FNPLL_delta_sigma_loop_0_0
// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
//               or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device      : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

(* CHECK_LICENSE_TYPE = "FNPLL_delta_sigma_loop_0_0,delta_sigma_loop,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "module_ref" *) 
(* x_core_info = "delta_sigma_loop,Vivado 2025.1" *) 
(* NotValidForBitStream *)
module FNPLL_delta_sigma_loop_0_0
   (clk,
    reset,
    filter_in,
    data_in,
    ctrl_out);
  (* x_interface_info = "xilinx.com:signal:clock:1.0 clk CLK" *) (* x_interface_mode = "slave clk" *) (* x_interface_parameter = "XIL_INTERFACENAME clk, ASSOCIATED_RESET reset, FREQ_HZ 55000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, INSERT_VIP 0" *) input clk;
  (* x_interface_info = "xilinx.com:signal:reset:1.0 reset RST" *) (* x_interface_mode = "slave reset" *) (* x_interface_parameter = "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input reset;
  input [15:0]filter_in;
  input [15:0]data_in;
  output ctrl_out;

  wire clk;
  wire ctrl_out;
  wire [15:0]data_in;
  wire reset;

  FNPLL_delta_sigma_loop_0_0_delta_sigma_loop U0
       (.clk(clk),
        .ctrl_out(ctrl_out),
        .data_in(data_in),
        .reset(reset));
endmodule

(* ORIG_REF_NAME = "delta_sigma_loop" *) 
module FNPLL_delta_sigma_loop_0_0_delta_sigma_loop
   (ctrl_out,
    data_in,
    reset,
    clk);
  output ctrl_out;
  input [15:0]data_in;
  input reset;
  input clk;

  wire \accumulator[11]_i_2_n_0 ;
  wire \accumulator[11]_i_3_n_0 ;
  wire \accumulator[11]_i_4_n_0 ;
  wire \accumulator[11]_i_5_n_0 ;
  wire \accumulator[15]_i_2_n_0 ;
  wire \accumulator[15]_i_3_n_0 ;
  wire \accumulator[15]_i_4_n_0 ;
  wire \accumulator[15]_i_5_n_0 ;
  wire \accumulator[3]_i_2_n_0 ;
  wire \accumulator[3]_i_3_n_0 ;
  wire \accumulator[3]_i_4_n_0 ;
  wire \accumulator[3]_i_5_n_0 ;
  wire \accumulator[7]_i_2_n_0 ;
  wire \accumulator[7]_i_3_n_0 ;
  wire \accumulator[7]_i_4_n_0 ;
  wire \accumulator[7]_i_5_n_0 ;
  wire \accumulator_reg[11]_i_1_n_0 ;
  wire \accumulator_reg[11]_i_1_n_1 ;
  wire \accumulator_reg[11]_i_1_n_2 ;
  wire \accumulator_reg[11]_i_1_n_3 ;
  wire \accumulator_reg[11]_i_1_n_4 ;
  wire \accumulator_reg[11]_i_1_n_5 ;
  wire \accumulator_reg[11]_i_1_n_6 ;
  wire \accumulator_reg[11]_i_1_n_7 ;
  wire \accumulator_reg[15]_i_1_n_0 ;
  wire \accumulator_reg[15]_i_1_n_1 ;
  wire \accumulator_reg[15]_i_1_n_2 ;
  wire \accumulator_reg[15]_i_1_n_3 ;
  wire \accumulator_reg[15]_i_1_n_4 ;
  wire \accumulator_reg[15]_i_1_n_5 ;
  wire \accumulator_reg[15]_i_1_n_6 ;
  wire \accumulator_reg[15]_i_1_n_7 ;
  wire \accumulator_reg[16]_i_1_n_3 ;
  wire \accumulator_reg[3]_i_1_n_0 ;
  wire \accumulator_reg[3]_i_1_n_1 ;
  wire \accumulator_reg[3]_i_1_n_2 ;
  wire \accumulator_reg[3]_i_1_n_3 ;
  wire \accumulator_reg[3]_i_1_n_4 ;
  wire \accumulator_reg[3]_i_1_n_5 ;
  wire \accumulator_reg[3]_i_1_n_6 ;
  wire \accumulator_reg[3]_i_1_n_7 ;
  wire \accumulator_reg[7]_i_1_n_0 ;
  wire \accumulator_reg[7]_i_1_n_1 ;
  wire \accumulator_reg[7]_i_1_n_2 ;
  wire \accumulator_reg[7]_i_1_n_3 ;
  wire \accumulator_reg[7]_i_1_n_4 ;
  wire \accumulator_reg[7]_i_1_n_5 ;
  wire \accumulator_reg[7]_i_1_n_6 ;
  wire \accumulator_reg[7]_i_1_n_7 ;
  wire \accumulator_reg_n_0_[0] ;
  wire \accumulator_reg_n_0_[10] ;
  wire \accumulator_reg_n_0_[11] ;
  wire \accumulator_reg_n_0_[12] ;
  wire \accumulator_reg_n_0_[13] ;
  wire \accumulator_reg_n_0_[14] ;
  wire \accumulator_reg_n_0_[15] ;
  wire \accumulator_reg_n_0_[1] ;
  wire \accumulator_reg_n_0_[2] ;
  wire \accumulator_reg_n_0_[3] ;
  wire \accumulator_reg_n_0_[4] ;
  wire \accumulator_reg_n_0_[5] ;
  wire \accumulator_reg_n_0_[6] ;
  wire \accumulator_reg_n_0_[7] ;
  wire \accumulator_reg_n_0_[8] ;
  wire \accumulator_reg_n_0_[9] ;
  wire clk;
  wire ctrl_out;
  wire [15:0]data_in;
  wire p_0_in;
  wire reset;
  wire [3:1]\NLW_accumulator_reg[16]_i_1_CO_UNCONNECTED ;
  wire [3:0]\NLW_accumulator_reg[16]_i_1_O_UNCONNECTED ;

  LUT2 #(
    .INIT(4'h6)) 
    \accumulator[11]_i_2 
       (.I0(data_in[11]),
        .I1(\accumulator_reg_n_0_[11] ),
        .O(\accumulator[11]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \accumulator[11]_i_3 
       (.I0(data_in[10]),
        .I1(\accumulator_reg_n_0_[10] ),
        .O(\accumulator[11]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \accumulator[11]_i_4 
       (.I0(data_in[9]),
        .I1(\accumulator_reg_n_0_[9] ),
        .O(\accumulator[11]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \accumulator[11]_i_5 
       (.I0(data_in[8]),
        .I1(\accumulator_reg_n_0_[8] ),
        .O(\accumulator[11]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \accumulator[15]_i_2 
       (.I0(\accumulator_reg_n_0_[15] ),
        .I1(data_in[15]),
        .O(\accumulator[15]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \accumulator[15]_i_3 
       (.I0(data_in[14]),
        .I1(\accumulator_reg_n_0_[14] ),
        .O(\accumulator[15]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \accumulator[15]_i_4 
       (.I0(data_in[13]),
        .I1(\accumulator_reg_n_0_[13] ),
        .O(\accumulator[15]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \accumulator[15]_i_5 
       (.I0(data_in[12]),
        .I1(\accumulator_reg_n_0_[12] ),
        .O(\accumulator[15]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \accumulator[3]_i_2 
       (.I0(data_in[3]),
        .I1(\accumulator_reg_n_0_[3] ),
        .O(\accumulator[3]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \accumulator[3]_i_3 
       (.I0(data_in[2]),
        .I1(\accumulator_reg_n_0_[2] ),
        .O(\accumulator[3]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \accumulator[3]_i_4 
       (.I0(data_in[1]),
        .I1(\accumulator_reg_n_0_[1] ),
        .O(\accumulator[3]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \accumulator[3]_i_5 
       (.I0(data_in[0]),
        .I1(\accumulator_reg_n_0_[0] ),
        .O(\accumulator[3]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \accumulator[7]_i_2 
       (.I0(data_in[7]),
        .I1(\accumulator_reg_n_0_[7] ),
        .O(\accumulator[7]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \accumulator[7]_i_3 
       (.I0(data_in[6]),
        .I1(\accumulator_reg_n_0_[6] ),
        .O(\accumulator[7]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \accumulator[7]_i_4 
       (.I0(data_in[5]),
        .I1(\accumulator_reg_n_0_[5] ),
        .O(\accumulator[7]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \accumulator[7]_i_5 
       (.I0(data_in[4]),
        .I1(\accumulator_reg_n_0_[4] ),
        .O(\accumulator[7]_i_5_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \accumulator_reg[0] 
       (.C(clk),
        .CE(1'b1),
        .D(\accumulator_reg[3]_i_1_n_7 ),
        .Q(\accumulator_reg_n_0_[0] ),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \accumulator_reg[10] 
       (.C(clk),
        .CE(1'b1),
        .D(\accumulator_reg[11]_i_1_n_5 ),
        .Q(\accumulator_reg_n_0_[10] ),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \accumulator_reg[11] 
       (.C(clk),
        .CE(1'b1),
        .D(\accumulator_reg[11]_i_1_n_4 ),
        .Q(\accumulator_reg_n_0_[11] ),
        .R(reset));
  CARRY4 \accumulator_reg[11]_i_1 
       (.CI(\accumulator_reg[7]_i_1_n_0 ),
        .CO({\accumulator_reg[11]_i_1_n_0 ,\accumulator_reg[11]_i_1_n_1 ,\accumulator_reg[11]_i_1_n_2 ,\accumulator_reg[11]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI(data_in[11:8]),
        .O({\accumulator_reg[11]_i_1_n_4 ,\accumulator_reg[11]_i_1_n_5 ,\accumulator_reg[11]_i_1_n_6 ,\accumulator_reg[11]_i_1_n_7 }),
        .S({\accumulator[11]_i_2_n_0 ,\accumulator[11]_i_3_n_0 ,\accumulator[11]_i_4_n_0 ,\accumulator[11]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \accumulator_reg[12] 
       (.C(clk),
        .CE(1'b1),
        .D(\accumulator_reg[15]_i_1_n_7 ),
        .Q(\accumulator_reg_n_0_[12] ),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \accumulator_reg[13] 
       (.C(clk),
        .CE(1'b1),
        .D(\accumulator_reg[15]_i_1_n_6 ),
        .Q(\accumulator_reg_n_0_[13] ),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \accumulator_reg[14] 
       (.C(clk),
        .CE(1'b1),
        .D(\accumulator_reg[15]_i_1_n_5 ),
        .Q(\accumulator_reg_n_0_[14] ),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \accumulator_reg[15] 
       (.C(clk),
        .CE(1'b1),
        .D(\accumulator_reg[15]_i_1_n_4 ),
        .Q(\accumulator_reg_n_0_[15] ),
        .R(reset));
  CARRY4 \accumulator_reg[15]_i_1 
       (.CI(\accumulator_reg[11]_i_1_n_0 ),
        .CO({\accumulator_reg[15]_i_1_n_0 ,\accumulator_reg[15]_i_1_n_1 ,\accumulator_reg[15]_i_1_n_2 ,\accumulator_reg[15]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({\accumulator_reg_n_0_[15] ,data_in[14:12]}),
        .O({\accumulator_reg[15]_i_1_n_4 ,\accumulator_reg[15]_i_1_n_5 ,\accumulator_reg[15]_i_1_n_6 ,\accumulator_reg[15]_i_1_n_7 }),
        .S({\accumulator[15]_i_2_n_0 ,\accumulator[15]_i_3_n_0 ,\accumulator[15]_i_4_n_0 ,\accumulator[15]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \accumulator_reg[16] 
       (.C(clk),
        .CE(1'b1),
        .D(\accumulator_reg[16]_i_1_n_3 ),
        .Q(p_0_in),
        .R(reset));
  CARRY4 \accumulator_reg[16]_i_1 
       (.CI(\accumulator_reg[15]_i_1_n_0 ),
        .CO({\NLW_accumulator_reg[16]_i_1_CO_UNCONNECTED [3:1],\accumulator_reg[16]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(\NLW_accumulator_reg[16]_i_1_O_UNCONNECTED [3:0]),
        .S({1'b0,1'b0,1'b0,1'b1}));
  FDRE #(
    .INIT(1'b0)) 
    \accumulator_reg[1] 
       (.C(clk),
        .CE(1'b1),
        .D(\accumulator_reg[3]_i_1_n_6 ),
        .Q(\accumulator_reg_n_0_[1] ),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \accumulator_reg[2] 
       (.C(clk),
        .CE(1'b1),
        .D(\accumulator_reg[3]_i_1_n_5 ),
        .Q(\accumulator_reg_n_0_[2] ),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \accumulator_reg[3] 
       (.C(clk),
        .CE(1'b1),
        .D(\accumulator_reg[3]_i_1_n_4 ),
        .Q(\accumulator_reg_n_0_[3] ),
        .R(reset));
  CARRY4 \accumulator_reg[3]_i_1 
       (.CI(1'b0),
        .CO({\accumulator_reg[3]_i_1_n_0 ,\accumulator_reg[3]_i_1_n_1 ,\accumulator_reg[3]_i_1_n_2 ,\accumulator_reg[3]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI(data_in[3:0]),
        .O({\accumulator_reg[3]_i_1_n_4 ,\accumulator_reg[3]_i_1_n_5 ,\accumulator_reg[3]_i_1_n_6 ,\accumulator_reg[3]_i_1_n_7 }),
        .S({\accumulator[3]_i_2_n_0 ,\accumulator[3]_i_3_n_0 ,\accumulator[3]_i_4_n_0 ,\accumulator[3]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \accumulator_reg[4] 
       (.C(clk),
        .CE(1'b1),
        .D(\accumulator_reg[7]_i_1_n_7 ),
        .Q(\accumulator_reg_n_0_[4] ),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \accumulator_reg[5] 
       (.C(clk),
        .CE(1'b1),
        .D(\accumulator_reg[7]_i_1_n_6 ),
        .Q(\accumulator_reg_n_0_[5] ),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \accumulator_reg[6] 
       (.C(clk),
        .CE(1'b1),
        .D(\accumulator_reg[7]_i_1_n_5 ),
        .Q(\accumulator_reg_n_0_[6] ),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \accumulator_reg[7] 
       (.C(clk),
        .CE(1'b1),
        .D(\accumulator_reg[7]_i_1_n_4 ),
        .Q(\accumulator_reg_n_0_[7] ),
        .R(reset));
  CARRY4 \accumulator_reg[7]_i_1 
       (.CI(\accumulator_reg[3]_i_1_n_0 ),
        .CO({\accumulator_reg[7]_i_1_n_0 ,\accumulator_reg[7]_i_1_n_1 ,\accumulator_reg[7]_i_1_n_2 ,\accumulator_reg[7]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI(data_in[7:4]),
        .O({\accumulator_reg[7]_i_1_n_4 ,\accumulator_reg[7]_i_1_n_5 ,\accumulator_reg[7]_i_1_n_6 ,\accumulator_reg[7]_i_1_n_7 }),
        .S({\accumulator[7]_i_2_n_0 ,\accumulator[7]_i_3_n_0 ,\accumulator[7]_i_4_n_0 ,\accumulator[7]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \accumulator_reg[8] 
       (.C(clk),
        .CE(1'b1),
        .D(\accumulator_reg[11]_i_1_n_7 ),
        .Q(\accumulator_reg_n_0_[8] ),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \accumulator_reg[9] 
       (.C(clk),
        .CE(1'b1),
        .D(\accumulator_reg[11]_i_1_n_6 ),
        .Q(\accumulator_reg_n_0_[9] ),
        .R(reset));
  FDRE ctrl_out_reg
       (.C(clk),
        .CE(1'b1),
        .D(p_0_in),
        .Q(ctrl_out),
        .R(reset));
endmodule
`ifndef GLBL
`define GLBL
`timescale  1 ps / 1 ps

module glbl ();

    parameter ROC_WIDTH = 100000;
    parameter TOC_WIDTH = 0;
    parameter GRES_WIDTH = 10000;
    parameter GRES_START = 10000;

//--------   STARTUP Globals --------------
    wire GSR;
    wire GTS;
    wire GWE;
    wire PRLD;
    wire GRESTORE;
    tri1 p_up_tmp;
    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;

    wire PROGB_GLBL;
    wire CCLKO_GLBL;
    wire FCSBO_GLBL;
    wire [3:0] DO_GLBL;
    wire [3:0] DI_GLBL;
   
    reg GSR_int;
    reg GTS_int;
    reg PRLD_int;
    reg GRESTORE_int;

//--------   JTAG Globals --------------
    wire JTAG_TDO_GLBL;
    wire JTAG_TCK_GLBL;
    wire JTAG_TDI_GLBL;
    wire JTAG_TMS_GLBL;
    wire JTAG_TRST_GLBL;

    reg JTAG_CAPTURE_GLBL;
    reg JTAG_RESET_GLBL;
    reg JTAG_SHIFT_GLBL;
    reg JTAG_UPDATE_GLBL;
    reg JTAG_RUNTEST_GLBL;

    reg JTAG_SEL1_GLBL = 0;
    reg JTAG_SEL2_GLBL = 0 ;
    reg JTAG_SEL3_GLBL = 0;
    reg JTAG_SEL4_GLBL = 0;

    reg JTAG_USER_TDO1_GLBL = 1'bz;
    reg JTAG_USER_TDO2_GLBL = 1'bz;
    reg JTAG_USER_TDO3_GLBL = 1'bz;
    reg JTAG_USER_TDO4_GLBL = 1'bz;

    assign (strong1, weak0) GSR = GSR_int;
    assign (strong1, weak0) GTS = GTS_int;
    assign (weak1, weak0) PRLD = PRLD_int;
    assign (strong1, weak0) GRESTORE = GRESTORE_int;

    initial begin
	GSR_int = 1'b1;
	PRLD_int = 1'b1;
	#(ROC_WIDTH)
	GSR_int = 1'b0;
	PRLD_int = 1'b0;
    end

    initial begin
	GTS_int = 1'b1;
	#(TOC_WIDTH)
	GTS_int = 1'b0;
    end

    initial begin 
	GRESTORE_int = 1'b0;
	#(GRES_START);
	GRESTORE_int = 1'b1;
	#(GRES_WIDTH);
	GRESTORE_int = 1'b0;
    end

endmodule
`endif
