-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2025.1 (win64) Build 6140274 Thu May 22 00:12:29 MDT 2025
-- Date        : Sat Dec 20 13:01:01 2025
-- Host        : LAPTOP-L3CRKKNJ running 64-bit major release  (build 9200)
-- Command     : write_vhdl -force -mode funcsim
--               c:/Vivado_Debug/FNPLL8/FNPLL2.gen/sources_1/bd/FNPLL/ip/FNPLL_filt_iir_0_0/FNPLL_filt_iir_0_0_sim_netlist.vhdl
-- Design      : FNPLL_filt_iir_0_0
-- Purpose     : This VHDL netlist is a functional simulation representation of the design and should not be modified or
--               synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device      : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity FNPLL_filt_iir_0_0_filt_iir is
  port (
    ctrl_out : out STD_LOGIC_VECTOR ( 15 downto 0 );
    reset : in STD_LOGIC;
    pulse_in : in STD_LOGIC;
    clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of FNPLL_filt_iir_0_0_filt_iir : entity is "filt_iir";
end FNPLL_filt_iir_0_0_filt_iir;

architecture STRUCTURE of FNPLL_filt_iir_0_0_filt_iir is
  signal \ARG_carry__0_i_1_n_0\ : STD_LOGIC;
  signal \ARG_carry__0_i_2_n_0\ : STD_LOGIC;
  signal \ARG_carry__0_i_3_n_0\ : STD_LOGIC;
  signal \ARG_carry__0_i_4_n_0\ : STD_LOGIC;
  signal \ARG_carry__0_n_0\ : STD_LOGIC;
  signal \ARG_carry__0_n_1\ : STD_LOGIC;
  signal \ARG_carry__0_n_2\ : STD_LOGIC;
  signal \ARG_carry__0_n_3\ : STD_LOGIC;
  signal \ARG_carry__1_i_1_n_0\ : STD_LOGIC;
  signal \ARG_carry__1_i_2_n_0\ : STD_LOGIC;
  signal \ARG_carry__1_i_3_n_0\ : STD_LOGIC;
  signal \ARG_carry__1_i_4_n_0\ : STD_LOGIC;
  signal \ARG_carry__1_n_0\ : STD_LOGIC;
  signal \ARG_carry__1_n_1\ : STD_LOGIC;
  signal \ARG_carry__1_n_2\ : STD_LOGIC;
  signal \ARG_carry__1_n_3\ : STD_LOGIC;
  signal \ARG_carry__1_n_4\ : STD_LOGIC;
  signal \ARG_carry__1_n_5\ : STD_LOGIC;
  signal \ARG_carry__2_i_1_n_0\ : STD_LOGIC;
  signal \ARG_carry__2_i_2_n_0\ : STD_LOGIC;
  signal \ARG_carry__2_i_3_n_0\ : STD_LOGIC;
  signal \ARG_carry__2_i_4_n_0\ : STD_LOGIC;
  signal \ARG_carry__2_n_0\ : STD_LOGIC;
  signal \ARG_carry__2_n_1\ : STD_LOGIC;
  signal \ARG_carry__2_n_2\ : STD_LOGIC;
  signal \ARG_carry__2_n_3\ : STD_LOGIC;
  signal \ARG_carry__2_n_4\ : STD_LOGIC;
  signal \ARG_carry__2_n_5\ : STD_LOGIC;
  signal \ARG_carry__2_n_6\ : STD_LOGIC;
  signal \ARG_carry__2_n_7\ : STD_LOGIC;
  signal \ARG_carry__3_i_1_n_0\ : STD_LOGIC;
  signal \ARG_carry__3_i_2_n_0\ : STD_LOGIC;
  signal \ARG_carry__3_i_3_n_0\ : STD_LOGIC;
  signal \ARG_carry__3_i_4_n_0\ : STD_LOGIC;
  signal \ARG_carry__3_n_0\ : STD_LOGIC;
  signal \ARG_carry__3_n_1\ : STD_LOGIC;
  signal \ARG_carry__3_n_2\ : STD_LOGIC;
  signal \ARG_carry__3_n_3\ : STD_LOGIC;
  signal \ARG_carry__3_n_4\ : STD_LOGIC;
  signal \ARG_carry__3_n_5\ : STD_LOGIC;
  signal \ARG_carry__3_n_6\ : STD_LOGIC;
  signal \ARG_carry__3_n_7\ : STD_LOGIC;
  signal \ARG_carry__4_i_1_n_0\ : STD_LOGIC;
  signal \ARG_carry__4_i_2_n_0\ : STD_LOGIC;
  signal \ARG_carry__4_i_3_n_0\ : STD_LOGIC;
  signal \ARG_carry__4_i_4_n_0\ : STD_LOGIC;
  signal \ARG_carry__4_n_0\ : STD_LOGIC;
  signal \ARG_carry__4_n_1\ : STD_LOGIC;
  signal \ARG_carry__4_n_2\ : STD_LOGIC;
  signal \ARG_carry__4_n_3\ : STD_LOGIC;
  signal \ARG_carry__4_n_4\ : STD_LOGIC;
  signal \ARG_carry__4_n_5\ : STD_LOGIC;
  signal \ARG_carry__4_n_6\ : STD_LOGIC;
  signal \ARG_carry__4_n_7\ : STD_LOGIC;
  signal \ARG_carry__5_i_1_n_0\ : STD_LOGIC;
  signal \ARG_carry__5_i_2_n_0\ : STD_LOGIC;
  signal \ARG_carry__5_i_3_n_0\ : STD_LOGIC;
  signal \ARG_carry__5_i_4_n_0\ : STD_LOGIC;
  signal \ARG_carry__5_n_0\ : STD_LOGIC;
  signal \ARG_carry__5_n_1\ : STD_LOGIC;
  signal \ARG_carry__5_n_2\ : STD_LOGIC;
  signal \ARG_carry__5_n_3\ : STD_LOGIC;
  signal \ARG_carry__5_n_4\ : STD_LOGIC;
  signal \ARG_carry__5_n_5\ : STD_LOGIC;
  signal \ARG_carry__5_n_6\ : STD_LOGIC;
  signal \ARG_carry__5_n_7\ : STD_LOGIC;
  signal \ARG_carry__6_i_1_n_0\ : STD_LOGIC;
  signal \ARG_carry__6_i_2_n_0\ : STD_LOGIC;
  signal \ARG_carry__6_i_3_n_0\ : STD_LOGIC;
  signal \ARG_carry__6_i_4_n_0\ : STD_LOGIC;
  signal \ARG_carry__6_n_1\ : STD_LOGIC;
  signal \ARG_carry__6_n_2\ : STD_LOGIC;
  signal \ARG_carry__6_n_3\ : STD_LOGIC;
  signal \ARG_carry__6_n_5\ : STD_LOGIC;
  signal \ARG_carry__6_n_6\ : STD_LOGIC;
  signal \ARG_carry__6_n_7\ : STD_LOGIC;
  signal ARG_carry_i_1_n_0 : STD_LOGIC;
  signal ARG_carry_i_2_n_0 : STD_LOGIC;
  signal ARG_carry_i_3_n_0 : STD_LOGIC;
  signal ARG_carry_i_4_n_0 : STD_LOGIC;
  signal ARG_carry_i_5_n_0 : STD_LOGIC;
  signal ARG_carry_n_0 : STD_LOGIC;
  signal ARG_carry_n_1 : STD_LOGIC;
  signal ARG_carry_n_2 : STD_LOGIC;
  signal ARG_carry_n_3 : STD_LOGIC;
  signal \accumulator[0]_i_2_n_0\ : STD_LOGIC;
  signal \accumulator[0]_i_3_n_0\ : STD_LOGIC;
  signal \accumulator[0]_i_4_n_0\ : STD_LOGIC;
  signal \accumulator[0]_i_5_n_0\ : STD_LOGIC;
  signal \accumulator[11]_i_2_n_0\ : STD_LOGIC;
  signal \accumulator[11]_i_3_n_0\ : STD_LOGIC;
  signal \accumulator[11]_i_4_n_0\ : STD_LOGIC;
  signal \accumulator[11]_i_5_n_0\ : STD_LOGIC;
  signal \accumulator[15]_i_2_n_0\ : STD_LOGIC;
  signal \accumulator[15]_i_3_n_0\ : STD_LOGIC;
  signal \accumulator[15]_i_4_n_0\ : STD_LOGIC;
  signal \accumulator[15]_i_5_n_0\ : STD_LOGIC;
  signal \accumulator[19]_i_2_n_0\ : STD_LOGIC;
  signal \accumulator[19]_i_3_n_0\ : STD_LOGIC;
  signal \accumulator[19]_i_4_n_0\ : STD_LOGIC;
  signal \accumulator[19]_i_5_n_0\ : STD_LOGIC;
  signal \accumulator[23]_i_2_n_0\ : STD_LOGIC;
  signal \accumulator[23]_i_3_n_0\ : STD_LOGIC;
  signal \accumulator[23]_i_4_n_0\ : STD_LOGIC;
  signal \accumulator[23]_i_5_n_0\ : STD_LOGIC;
  signal \accumulator[25]_i_2_n_0\ : STD_LOGIC;
  signal \accumulator[25]_i_3_n_0\ : STD_LOGIC;
  signal \accumulator[25]_i_4_n_0\ : STD_LOGIC;
  signal \accumulator[25]_i_5_n_0\ : STD_LOGIC;
  signal \accumulator[28]_i_2_n_0\ : STD_LOGIC;
  signal \accumulator[28]_i_3_n_0\ : STD_LOGIC;
  signal \accumulator[28]_i_4_n_0\ : STD_LOGIC;
  signal \accumulator[28]_i_5_n_0\ : STD_LOGIC;
  signal \accumulator[4]_i_2_n_0\ : STD_LOGIC;
  signal \accumulator[4]_i_3_n_0\ : STD_LOGIC;
  signal \accumulator[4]_i_4_n_0\ : STD_LOGIC;
  signal \accumulator[4]_i_5_n_0\ : STD_LOGIC;
  signal accumulator_reg : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal \accumulator_reg[0]_i_1_n_0\ : STD_LOGIC;
  signal \accumulator_reg[0]_i_1_n_1\ : STD_LOGIC;
  signal \accumulator_reg[0]_i_1_n_2\ : STD_LOGIC;
  signal \accumulator_reg[0]_i_1_n_3\ : STD_LOGIC;
  signal \accumulator_reg[0]_i_1_n_4\ : STD_LOGIC;
  signal \accumulator_reg[0]_i_1_n_5\ : STD_LOGIC;
  signal \accumulator_reg[0]_i_1_n_6\ : STD_LOGIC;
  signal \accumulator_reg[0]_i_1_n_7\ : STD_LOGIC;
  signal \accumulator_reg[11]_i_1_n_0\ : STD_LOGIC;
  signal \accumulator_reg[11]_i_1_n_1\ : STD_LOGIC;
  signal \accumulator_reg[11]_i_1_n_2\ : STD_LOGIC;
  signal \accumulator_reg[11]_i_1_n_3\ : STD_LOGIC;
  signal \accumulator_reg[11]_i_1_n_4\ : STD_LOGIC;
  signal \accumulator_reg[11]_i_1_n_5\ : STD_LOGIC;
  signal \accumulator_reg[11]_i_1_n_6\ : STD_LOGIC;
  signal \accumulator_reg[11]_i_1_n_7\ : STD_LOGIC;
  signal \accumulator_reg[15]_i_1_n_0\ : STD_LOGIC;
  signal \accumulator_reg[15]_i_1_n_1\ : STD_LOGIC;
  signal \accumulator_reg[15]_i_1_n_2\ : STD_LOGIC;
  signal \accumulator_reg[15]_i_1_n_3\ : STD_LOGIC;
  signal \accumulator_reg[15]_i_1_n_4\ : STD_LOGIC;
  signal \accumulator_reg[15]_i_1_n_5\ : STD_LOGIC;
  signal \accumulator_reg[15]_i_1_n_6\ : STD_LOGIC;
  signal \accumulator_reg[15]_i_1_n_7\ : STD_LOGIC;
  signal \accumulator_reg[19]_i_1_n_0\ : STD_LOGIC;
  signal \accumulator_reg[19]_i_1_n_1\ : STD_LOGIC;
  signal \accumulator_reg[19]_i_1_n_2\ : STD_LOGIC;
  signal \accumulator_reg[19]_i_1_n_3\ : STD_LOGIC;
  signal \accumulator_reg[19]_i_1_n_4\ : STD_LOGIC;
  signal \accumulator_reg[19]_i_1_n_5\ : STD_LOGIC;
  signal \accumulator_reg[19]_i_1_n_6\ : STD_LOGIC;
  signal \accumulator_reg[19]_i_1_n_7\ : STD_LOGIC;
  signal \accumulator_reg[23]_i_1_n_0\ : STD_LOGIC;
  signal \accumulator_reg[23]_i_1_n_1\ : STD_LOGIC;
  signal \accumulator_reg[23]_i_1_n_2\ : STD_LOGIC;
  signal \accumulator_reg[23]_i_1_n_3\ : STD_LOGIC;
  signal \accumulator_reg[23]_i_1_n_4\ : STD_LOGIC;
  signal \accumulator_reg[23]_i_1_n_5\ : STD_LOGIC;
  signal \accumulator_reg[23]_i_1_n_6\ : STD_LOGIC;
  signal \accumulator_reg[23]_i_1_n_7\ : STD_LOGIC;
  signal \accumulator_reg[25]_i_1_n_0\ : STD_LOGIC;
  signal \accumulator_reg[25]_i_1_n_1\ : STD_LOGIC;
  signal \accumulator_reg[25]_i_1_n_2\ : STD_LOGIC;
  signal \accumulator_reg[25]_i_1_n_3\ : STD_LOGIC;
  signal \accumulator_reg[25]_i_1_n_4\ : STD_LOGIC;
  signal \accumulator_reg[25]_i_1_n_5\ : STD_LOGIC;
  signal \accumulator_reg[25]_i_1_n_6\ : STD_LOGIC;
  signal \accumulator_reg[25]_i_1_n_7\ : STD_LOGIC;
  signal \accumulator_reg[28]_i_1_n_1\ : STD_LOGIC;
  signal \accumulator_reg[28]_i_1_n_2\ : STD_LOGIC;
  signal \accumulator_reg[28]_i_1_n_3\ : STD_LOGIC;
  signal \accumulator_reg[28]_i_1_n_4\ : STD_LOGIC;
  signal \accumulator_reg[28]_i_1_n_5\ : STD_LOGIC;
  signal \accumulator_reg[28]_i_1_n_6\ : STD_LOGIC;
  signal \accumulator_reg[28]_i_1_n_7\ : STD_LOGIC;
  signal \accumulator_reg[4]_i_1_n_0\ : STD_LOGIC;
  signal \accumulator_reg[4]_i_1_n_1\ : STD_LOGIC;
  signal \accumulator_reg[4]_i_1_n_2\ : STD_LOGIC;
  signal \accumulator_reg[4]_i_1_n_3\ : STD_LOGIC;
  signal \accumulator_reg[4]_i_1_n_4\ : STD_LOGIC;
  signal \accumulator_reg[4]_i_1_n_5\ : STD_LOGIC;
  signal \accumulator_reg[4]_i_1_n_6\ : STD_LOGIC;
  signal \accumulator_reg[4]_i_1_n_7\ : STD_LOGIC;
  signal \^ctrl_out\ : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal in0 : STD_LOGIC;
  signal pulse_sync1 : STD_LOGIC;
  signal pulse_sync2 : STD_LOGIC;
  signal NLW_ARG_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_ARG_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_ARG_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_ARG_carry__6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \NLW_accumulator_reg[28]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  attribute ADDER_THRESHOLD : integer;
  attribute ADDER_THRESHOLD of ARG_carry : label is 35;
  attribute ADDER_THRESHOLD of \ARG_carry__0\ : label is 35;
  attribute ADDER_THRESHOLD of \ARG_carry__1\ : label is 35;
  attribute ADDER_THRESHOLD of \ARG_carry__2\ : label is 35;
  attribute ADDER_THRESHOLD of \ARG_carry__3\ : label is 35;
  attribute ADDER_THRESHOLD of \ARG_carry__4\ : label is 35;
  attribute ADDER_THRESHOLD of \ARG_carry__5\ : label is 35;
  attribute ADDER_THRESHOLD of \ARG_carry__6\ : label is 35;
  attribute ADDER_THRESHOLD of \accumulator_reg[0]_i_1\ : label is 11;
  attribute ADDER_THRESHOLD of \accumulator_reg[11]_i_1\ : label is 11;
  attribute ADDER_THRESHOLD of \accumulator_reg[15]_i_1\ : label is 11;
  attribute ADDER_THRESHOLD of \accumulator_reg[19]_i_1\ : label is 11;
  attribute ADDER_THRESHOLD of \accumulator_reg[23]_i_1\ : label is 11;
  attribute ADDER_THRESHOLD of \accumulator_reg[25]_i_1\ : label is 11;
  attribute ADDER_THRESHOLD of \accumulator_reg[28]_i_1\ : label is 11;
  attribute ADDER_THRESHOLD of \accumulator_reg[4]_i_1\ : label is 11;
begin
  ctrl_out(15 downto 0) <= \^ctrl_out\(15 downto 0);
ARG_carry: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => ARG_carry_n_0,
      CO(2) => ARG_carry_n_1,
      CO(1) => ARG_carry_n_2,
      CO(0) => ARG_carry_n_3,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1) => ARG_carry_i_1_n_0,
      DI(0) => '0',
      O(3 downto 0) => NLW_ARG_carry_O_UNCONNECTED(3 downto 0),
      S(3) => ARG_carry_i_2_n_0,
      S(2) => ARG_carry_i_3_n_0,
      S(1) => ARG_carry_i_4_n_0,
      S(0) => ARG_carry_i_5_n_0
    );
\ARG_carry__0\: unisim.vcomponents.CARRY4
     port map (
      CI => ARG_carry_n_0,
      CO(3) => \ARG_carry__0_n_0\,
      CO(2) => \ARG_carry__0_n_1\,
      CO(1) => \ARG_carry__0_n_2\,
      CO(0) => \ARG_carry__0_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \NLW_ARG_carry__0_O_UNCONNECTED\(3 downto 0),
      S(3) => \ARG_carry__0_i_1_n_0\,
      S(2) => \ARG_carry__0_i_2_n_0\,
      S(1) => \ARG_carry__0_i_3_n_0\,
      S(0) => \ARG_carry__0_i_4_n_0\
    );
\ARG_carry__0_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => accumulator_reg(7),
      O => \ARG_carry__0_i_1_n_0\
    );
\ARG_carry__0_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => accumulator_reg(6),
      O => \ARG_carry__0_i_2_n_0\
    );
\ARG_carry__0_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => accumulator_reg(5),
      O => \ARG_carry__0_i_3_n_0\
    );
\ARG_carry__0_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => accumulator_reg(4),
      O => \ARG_carry__0_i_4_n_0\
    );
\ARG_carry__1\: unisim.vcomponents.CARRY4
     port map (
      CI => \ARG_carry__0_n_0\,
      CO(3) => \ARG_carry__1_n_0\,
      CO(2) => \ARG_carry__1_n_1\,
      CO(1) => \ARG_carry__1_n_2\,
      CO(0) => \ARG_carry__1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \ARG_carry__1_n_4\,
      O(2) => \ARG_carry__1_n_5\,
      O(1 downto 0) => \NLW_ARG_carry__1_O_UNCONNECTED\(1 downto 0),
      S(3) => \ARG_carry__1_i_1_n_0\,
      S(2) => \ARG_carry__1_i_2_n_0\,
      S(1) => \ARG_carry__1_i_3_n_0\,
      S(0) => \ARG_carry__1_i_4_n_0\
    );
\ARG_carry__1_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^ctrl_out\(1),
      O => \ARG_carry__1_i_1_n_0\
    );
\ARG_carry__1_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^ctrl_out\(0),
      O => \ARG_carry__1_i_2_n_0\
    );
\ARG_carry__1_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => accumulator_reg(9),
      O => \ARG_carry__1_i_3_n_0\
    );
\ARG_carry__1_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => accumulator_reg(8),
      O => \ARG_carry__1_i_4_n_0\
    );
\ARG_carry__2\: unisim.vcomponents.CARRY4
     port map (
      CI => \ARG_carry__1_n_0\,
      CO(3) => \ARG_carry__2_n_0\,
      CO(2) => \ARG_carry__2_n_1\,
      CO(1) => \ARG_carry__2_n_2\,
      CO(0) => \ARG_carry__2_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \ARG_carry__2_n_4\,
      O(2) => \ARG_carry__2_n_5\,
      O(1) => \ARG_carry__2_n_6\,
      O(0) => \ARG_carry__2_n_7\,
      S(3) => \ARG_carry__2_i_1_n_0\,
      S(2) => \ARG_carry__2_i_2_n_0\,
      S(1) => \ARG_carry__2_i_3_n_0\,
      S(0) => \ARG_carry__2_i_4_n_0\
    );
\ARG_carry__2_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^ctrl_out\(5),
      O => \ARG_carry__2_i_1_n_0\
    );
\ARG_carry__2_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^ctrl_out\(4),
      O => \ARG_carry__2_i_2_n_0\
    );
\ARG_carry__2_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^ctrl_out\(3),
      O => \ARG_carry__2_i_3_n_0\
    );
\ARG_carry__2_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^ctrl_out\(2),
      O => \ARG_carry__2_i_4_n_0\
    );
\ARG_carry__3\: unisim.vcomponents.CARRY4
     port map (
      CI => \ARG_carry__2_n_0\,
      CO(3) => \ARG_carry__3_n_0\,
      CO(2) => \ARG_carry__3_n_1\,
      CO(1) => \ARG_carry__3_n_2\,
      CO(0) => \ARG_carry__3_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \ARG_carry__3_n_4\,
      O(2) => \ARG_carry__3_n_5\,
      O(1) => \ARG_carry__3_n_6\,
      O(0) => \ARG_carry__3_n_7\,
      S(3) => \ARG_carry__3_i_1_n_0\,
      S(2) => \ARG_carry__3_i_2_n_0\,
      S(1) => \ARG_carry__3_i_3_n_0\,
      S(0) => \ARG_carry__3_i_4_n_0\
    );
\ARG_carry__3_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^ctrl_out\(9),
      O => \ARG_carry__3_i_1_n_0\
    );
\ARG_carry__3_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^ctrl_out\(8),
      O => \ARG_carry__3_i_2_n_0\
    );
\ARG_carry__3_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^ctrl_out\(7),
      O => \ARG_carry__3_i_3_n_0\
    );
\ARG_carry__3_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^ctrl_out\(6),
      O => \ARG_carry__3_i_4_n_0\
    );
\ARG_carry__4\: unisim.vcomponents.CARRY4
     port map (
      CI => \ARG_carry__3_n_0\,
      CO(3) => \ARG_carry__4_n_0\,
      CO(2) => \ARG_carry__4_n_1\,
      CO(1) => \ARG_carry__4_n_2\,
      CO(0) => \ARG_carry__4_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \ARG_carry__4_n_4\,
      O(2) => \ARG_carry__4_n_5\,
      O(1) => \ARG_carry__4_n_6\,
      O(0) => \ARG_carry__4_n_7\,
      S(3) => \ARG_carry__4_i_1_n_0\,
      S(2) => \ARG_carry__4_i_2_n_0\,
      S(1) => \ARG_carry__4_i_3_n_0\,
      S(0) => \ARG_carry__4_i_4_n_0\
    );
\ARG_carry__4_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^ctrl_out\(13),
      O => \ARG_carry__4_i_1_n_0\
    );
\ARG_carry__4_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^ctrl_out\(12),
      O => \ARG_carry__4_i_2_n_0\
    );
\ARG_carry__4_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^ctrl_out\(11),
      O => \ARG_carry__4_i_3_n_0\
    );
\ARG_carry__4_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^ctrl_out\(10),
      O => \ARG_carry__4_i_4_n_0\
    );
\ARG_carry__5\: unisim.vcomponents.CARRY4
     port map (
      CI => \ARG_carry__4_n_0\,
      CO(3) => \ARG_carry__5_n_0\,
      CO(2) => \ARG_carry__5_n_1\,
      CO(1) => \ARG_carry__5_n_2\,
      CO(0) => \ARG_carry__5_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \ARG_carry__5_n_4\,
      O(2) => \ARG_carry__5_n_5\,
      O(1) => \ARG_carry__5_n_6\,
      O(0) => \ARG_carry__5_n_7\,
      S(3) => \ARG_carry__5_i_1_n_0\,
      S(2) => \ARG_carry__5_i_2_n_0\,
      S(1) => \ARG_carry__5_i_3_n_0\,
      S(0) => \ARG_carry__5_i_4_n_0\
    );
\ARG_carry__5_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => accumulator_reg(27),
      O => \ARG_carry__5_i_1_n_0\
    );
\ARG_carry__5_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => accumulator_reg(26),
      O => \ARG_carry__5_i_2_n_0\
    );
\ARG_carry__5_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^ctrl_out\(15),
      O => \ARG_carry__5_i_3_n_0\
    );
\ARG_carry__5_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^ctrl_out\(14),
      O => \ARG_carry__5_i_4_n_0\
    );
\ARG_carry__6\: unisim.vcomponents.CARRY4
     port map (
      CI => \ARG_carry__5_n_0\,
      CO(3) => \NLW_ARG_carry__6_CO_UNCONNECTED\(3),
      CO(2) => \ARG_carry__6_n_1\,
      CO(1) => \ARG_carry__6_n_2\,
      CO(0) => \ARG_carry__6_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => in0,
      O(2) => \ARG_carry__6_n_5\,
      O(1) => \ARG_carry__6_n_6\,
      O(0) => \ARG_carry__6_n_7\,
      S(3) => \ARG_carry__6_i_1_n_0\,
      S(2) => \ARG_carry__6_i_2_n_0\,
      S(1) => \ARG_carry__6_i_3_n_0\,
      S(0) => \ARG_carry__6_i_4_n_0\
    );
\ARG_carry__6_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => accumulator_reg(31),
      O => \ARG_carry__6_i_1_n_0\
    );
\ARG_carry__6_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => accumulator_reg(30),
      O => \ARG_carry__6_i_2_n_0\
    );
\ARG_carry__6_i_3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => accumulator_reg(29),
      O => \ARG_carry__6_i_3_n_0\
    );
\ARG_carry__6_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => accumulator_reg(28),
      O => \ARG_carry__6_i_4_n_0\
    );
ARG_carry_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => pulse_sync2,
      I1 => accumulator_reg(0),
      O => ARG_carry_i_1_n_0
    );
ARG_carry_i_2: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => accumulator_reg(3),
      O => ARG_carry_i_2_n_0
    );
ARG_carry_i_3: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => accumulator_reg(2),
      O => ARG_carry_i_3_n_0
    );
ARG_carry_i_4: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D2"
    )
        port map (
      I0 => accumulator_reg(0),
      I1 => pulse_sync2,
      I2 => accumulator_reg(1),
      O => ARG_carry_i_4_n_0
    );
ARG_carry_i_5: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => pulse_sync2,
      I1 => accumulator_reg(0),
      O => ARG_carry_i_5_n_0
    );
\accumulator[0]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \ARG_carry__2_n_6\,
      I1 => accumulator_reg(3),
      O => \accumulator[0]_i_2_n_0\
    );
\accumulator[0]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \ARG_carry__2_n_7\,
      I1 => accumulator_reg(2),
      O => \accumulator[0]_i_3_n_0\
    );
\accumulator[0]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \ARG_carry__1_n_4\,
      I1 => accumulator_reg(1),
      O => \accumulator[0]_i_4_n_0\
    );
\accumulator[0]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \ARG_carry__1_n_5\,
      I1 => accumulator_reg(0),
      O => \accumulator[0]_i_5_n_0\
    );
\accumulator[11]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \ARG_carry__4_n_6\,
      I1 => \^ctrl_out\(1),
      O => \accumulator[11]_i_2_n_0\
    );
\accumulator[11]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \ARG_carry__4_n_7\,
      I1 => \^ctrl_out\(0),
      O => \accumulator[11]_i_3_n_0\
    );
\accumulator[11]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \ARG_carry__3_n_4\,
      I1 => accumulator_reg(9),
      O => \accumulator[11]_i_4_n_0\
    );
\accumulator[11]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \ARG_carry__3_n_5\,
      I1 => accumulator_reg(8),
      O => \accumulator[11]_i_5_n_0\
    );
\accumulator[15]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \ARG_carry__5_n_6\,
      I1 => \^ctrl_out\(5),
      O => \accumulator[15]_i_2_n_0\
    );
\accumulator[15]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \ARG_carry__5_n_7\,
      I1 => \^ctrl_out\(4),
      O => \accumulator[15]_i_3_n_0\
    );
\accumulator[15]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \ARG_carry__4_n_4\,
      I1 => \^ctrl_out\(3),
      O => \accumulator[15]_i_4_n_0\
    );
\accumulator[15]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \ARG_carry__4_n_5\,
      I1 => \^ctrl_out\(2),
      O => \accumulator[15]_i_5_n_0\
    );
\accumulator[19]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \ARG_carry__6_n_6\,
      I1 => \^ctrl_out\(9),
      O => \accumulator[19]_i_2_n_0\
    );
\accumulator[19]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \ARG_carry__6_n_7\,
      I1 => \^ctrl_out\(8),
      O => \accumulator[19]_i_3_n_0\
    );
\accumulator[19]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \ARG_carry__5_n_4\,
      I1 => \^ctrl_out\(7),
      O => \accumulator[19]_i_4_n_0\
    );
\accumulator[19]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \ARG_carry__5_n_5\,
      I1 => \^ctrl_out\(6),
      O => \accumulator[19]_i_5_n_0\
    );
\accumulator[23]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => in0,
      I1 => \^ctrl_out\(13),
      O => \accumulator[23]_i_2_n_0\
    );
\accumulator[23]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => in0,
      I1 => \^ctrl_out\(12),
      O => \accumulator[23]_i_3_n_0\
    );
\accumulator[23]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => in0,
      I1 => \^ctrl_out\(11),
      O => \accumulator[23]_i_4_n_0\
    );
\accumulator[23]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \ARG_carry__6_n_5\,
      I1 => \^ctrl_out\(10),
      O => \accumulator[23]_i_5_n_0\
    );
\accumulator[25]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => in0,
      I1 => accumulator_reg(27),
      O => \accumulator[25]_i_2_n_0\
    );
\accumulator[25]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => in0,
      I1 => accumulator_reg(26),
      O => \accumulator[25]_i_3_n_0\
    );
\accumulator[25]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => in0,
      I1 => \^ctrl_out\(15),
      O => \accumulator[25]_i_4_n_0\
    );
\accumulator[25]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => in0,
      I1 => \^ctrl_out\(14),
      O => \accumulator[25]_i_5_n_0\
    );
\accumulator[28]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => in0,
      I1 => accumulator_reg(31),
      O => \accumulator[28]_i_2_n_0\
    );
\accumulator[28]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => in0,
      I1 => accumulator_reg(30),
      O => \accumulator[28]_i_3_n_0\
    );
\accumulator[28]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => in0,
      I1 => accumulator_reg(29),
      O => \accumulator[28]_i_4_n_0\
    );
\accumulator[28]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => in0,
      I1 => accumulator_reg(28),
      O => \accumulator[28]_i_5_n_0\
    );
\accumulator[4]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \ARG_carry__3_n_6\,
      I1 => accumulator_reg(7),
      O => \accumulator[4]_i_2_n_0\
    );
\accumulator[4]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \ARG_carry__3_n_7\,
      I1 => accumulator_reg(6),
      O => \accumulator[4]_i_3_n_0\
    );
\accumulator[4]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \ARG_carry__2_n_4\,
      I1 => accumulator_reg(5),
      O => \accumulator[4]_i_4_n_0\
    );
\accumulator[4]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => \ARG_carry__2_n_5\,
      I1 => accumulator_reg(4),
      O => \accumulator[4]_i_5_n_0\
    );
\accumulator_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \accumulator_reg[0]_i_1_n_7\,
      Q => accumulator_reg(0),
      R => reset
    );
\accumulator_reg[0]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \accumulator_reg[0]_i_1_n_0\,
      CO(2) => \accumulator_reg[0]_i_1_n_1\,
      CO(1) => \accumulator_reg[0]_i_1_n_2\,
      CO(0) => \accumulator_reg[0]_i_1_n_3\,
      CYINIT => '0',
      DI(3) => \ARG_carry__2_n_6\,
      DI(2) => \ARG_carry__2_n_7\,
      DI(1) => \ARG_carry__1_n_4\,
      DI(0) => \ARG_carry__1_n_5\,
      O(3) => \accumulator_reg[0]_i_1_n_4\,
      O(2) => \accumulator_reg[0]_i_1_n_5\,
      O(1) => \accumulator_reg[0]_i_1_n_6\,
      O(0) => \accumulator_reg[0]_i_1_n_7\,
      S(3) => \accumulator[0]_i_2_n_0\,
      S(2) => \accumulator[0]_i_3_n_0\,
      S(1) => \accumulator[0]_i_4_n_0\,
      S(0) => \accumulator[0]_i_5_n_0\
    );
\accumulator_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \accumulator_reg[11]_i_1_n_5\,
      Q => \^ctrl_out\(0),
      R => reset
    );
\accumulator_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \accumulator_reg[11]_i_1_n_4\,
      Q => \^ctrl_out\(1),
      R => reset
    );
\accumulator_reg[11]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \accumulator_reg[4]_i_1_n_0\,
      CO(3) => \accumulator_reg[11]_i_1_n_0\,
      CO(2) => \accumulator_reg[11]_i_1_n_1\,
      CO(1) => \accumulator_reg[11]_i_1_n_2\,
      CO(0) => \accumulator_reg[11]_i_1_n_3\,
      CYINIT => '0',
      DI(3) => \ARG_carry__4_n_6\,
      DI(2) => \ARG_carry__4_n_7\,
      DI(1) => \ARG_carry__3_n_4\,
      DI(0) => \ARG_carry__3_n_5\,
      O(3) => \accumulator_reg[11]_i_1_n_4\,
      O(2) => \accumulator_reg[11]_i_1_n_5\,
      O(1) => \accumulator_reg[11]_i_1_n_6\,
      O(0) => \accumulator_reg[11]_i_1_n_7\,
      S(3) => \accumulator[11]_i_2_n_0\,
      S(2) => \accumulator[11]_i_3_n_0\,
      S(1) => \accumulator[11]_i_4_n_0\,
      S(0) => \accumulator[11]_i_5_n_0\
    );
\accumulator_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \accumulator_reg[15]_i_1_n_7\,
      Q => \^ctrl_out\(2),
      R => reset
    );
\accumulator_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \accumulator_reg[15]_i_1_n_6\,
      Q => \^ctrl_out\(3),
      R => reset
    );
\accumulator_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \accumulator_reg[15]_i_1_n_5\,
      Q => \^ctrl_out\(4),
      R => reset
    );
\accumulator_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \accumulator_reg[15]_i_1_n_4\,
      Q => \^ctrl_out\(5),
      R => reset
    );
\accumulator_reg[15]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \accumulator_reg[11]_i_1_n_0\,
      CO(3) => \accumulator_reg[15]_i_1_n_0\,
      CO(2) => \accumulator_reg[15]_i_1_n_1\,
      CO(1) => \accumulator_reg[15]_i_1_n_2\,
      CO(0) => \accumulator_reg[15]_i_1_n_3\,
      CYINIT => '0',
      DI(3) => \ARG_carry__5_n_6\,
      DI(2) => \ARG_carry__5_n_7\,
      DI(1) => \ARG_carry__4_n_4\,
      DI(0) => \ARG_carry__4_n_5\,
      O(3) => \accumulator_reg[15]_i_1_n_4\,
      O(2) => \accumulator_reg[15]_i_1_n_5\,
      O(1) => \accumulator_reg[15]_i_1_n_6\,
      O(0) => \accumulator_reg[15]_i_1_n_7\,
      S(3) => \accumulator[15]_i_2_n_0\,
      S(2) => \accumulator[15]_i_3_n_0\,
      S(1) => \accumulator[15]_i_4_n_0\,
      S(0) => \accumulator[15]_i_5_n_0\
    );
\accumulator_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \accumulator_reg[19]_i_1_n_7\,
      Q => \^ctrl_out\(6),
      R => reset
    );
\accumulator_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \accumulator_reg[19]_i_1_n_6\,
      Q => \^ctrl_out\(7),
      R => reset
    );
\accumulator_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \accumulator_reg[19]_i_1_n_5\,
      Q => \^ctrl_out\(8),
      R => reset
    );
\accumulator_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \accumulator_reg[19]_i_1_n_4\,
      Q => \^ctrl_out\(9),
      R => reset
    );
\accumulator_reg[19]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \accumulator_reg[15]_i_1_n_0\,
      CO(3) => \accumulator_reg[19]_i_1_n_0\,
      CO(2) => \accumulator_reg[19]_i_1_n_1\,
      CO(1) => \accumulator_reg[19]_i_1_n_2\,
      CO(0) => \accumulator_reg[19]_i_1_n_3\,
      CYINIT => '0',
      DI(3) => \ARG_carry__6_n_6\,
      DI(2) => \ARG_carry__6_n_7\,
      DI(1) => \ARG_carry__5_n_4\,
      DI(0) => \ARG_carry__5_n_5\,
      O(3) => \accumulator_reg[19]_i_1_n_4\,
      O(2) => \accumulator_reg[19]_i_1_n_5\,
      O(1) => \accumulator_reg[19]_i_1_n_6\,
      O(0) => \accumulator_reg[19]_i_1_n_7\,
      S(3) => \accumulator[19]_i_2_n_0\,
      S(2) => \accumulator[19]_i_3_n_0\,
      S(1) => \accumulator[19]_i_4_n_0\,
      S(0) => \accumulator[19]_i_5_n_0\
    );
\accumulator_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \accumulator_reg[0]_i_1_n_6\,
      Q => accumulator_reg(1),
      R => reset
    );
\accumulator_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \accumulator_reg[23]_i_1_n_7\,
      Q => \^ctrl_out\(10),
      R => reset
    );
\accumulator_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \accumulator_reg[23]_i_1_n_6\,
      Q => \^ctrl_out\(11),
      R => reset
    );
\accumulator_reg[22]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \accumulator_reg[23]_i_1_n_5\,
      Q => \^ctrl_out\(12),
      R => reset
    );
\accumulator_reg[23]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \accumulator_reg[23]_i_1_n_4\,
      Q => \^ctrl_out\(13),
      R => reset
    );
\accumulator_reg[23]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \accumulator_reg[19]_i_1_n_0\,
      CO(3) => \accumulator_reg[23]_i_1_n_0\,
      CO(2) => \accumulator_reg[23]_i_1_n_1\,
      CO(1) => \accumulator_reg[23]_i_1_n_2\,
      CO(0) => \accumulator_reg[23]_i_1_n_3\,
      CYINIT => '0',
      DI(3) => in0,
      DI(2) => in0,
      DI(1) => in0,
      DI(0) => \ARG_carry__6_n_5\,
      O(3) => \accumulator_reg[23]_i_1_n_4\,
      O(2) => \accumulator_reg[23]_i_1_n_5\,
      O(1) => \accumulator_reg[23]_i_1_n_6\,
      O(0) => \accumulator_reg[23]_i_1_n_7\,
      S(3) => \accumulator[23]_i_2_n_0\,
      S(2) => \accumulator[23]_i_3_n_0\,
      S(1) => \accumulator[23]_i_4_n_0\,
      S(0) => \accumulator[23]_i_5_n_0\
    );
\accumulator_reg[24]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \accumulator_reg[25]_i_1_n_7\,
      Q => \^ctrl_out\(14),
      R => reset
    );
\accumulator_reg[25]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \accumulator_reg[25]_i_1_n_6\,
      Q => \^ctrl_out\(15),
      R => reset
    );
\accumulator_reg[25]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \accumulator_reg[23]_i_1_n_0\,
      CO(3) => \accumulator_reg[25]_i_1_n_0\,
      CO(2) => \accumulator_reg[25]_i_1_n_1\,
      CO(1) => \accumulator_reg[25]_i_1_n_2\,
      CO(0) => \accumulator_reg[25]_i_1_n_3\,
      CYINIT => '0',
      DI(3) => in0,
      DI(2) => in0,
      DI(1) => in0,
      DI(0) => in0,
      O(3) => \accumulator_reg[25]_i_1_n_4\,
      O(2) => \accumulator_reg[25]_i_1_n_5\,
      O(1) => \accumulator_reg[25]_i_1_n_6\,
      O(0) => \accumulator_reg[25]_i_1_n_7\,
      S(3) => \accumulator[25]_i_2_n_0\,
      S(2) => \accumulator[25]_i_3_n_0\,
      S(1) => \accumulator[25]_i_4_n_0\,
      S(0) => \accumulator[25]_i_5_n_0\
    );
\accumulator_reg[26]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \accumulator_reg[25]_i_1_n_5\,
      Q => accumulator_reg(26),
      R => reset
    );
\accumulator_reg[27]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \accumulator_reg[25]_i_1_n_4\,
      Q => accumulator_reg(27),
      R => reset
    );
\accumulator_reg[28]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \accumulator_reg[28]_i_1_n_7\,
      Q => accumulator_reg(28),
      R => reset
    );
\accumulator_reg[28]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \accumulator_reg[25]_i_1_n_0\,
      CO(3) => \NLW_accumulator_reg[28]_i_1_CO_UNCONNECTED\(3),
      CO(2) => \accumulator_reg[28]_i_1_n_1\,
      CO(1) => \accumulator_reg[28]_i_1_n_2\,
      CO(0) => \accumulator_reg[28]_i_1_n_3\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => in0,
      DI(1) => in0,
      DI(0) => in0,
      O(3) => \accumulator_reg[28]_i_1_n_4\,
      O(2) => \accumulator_reg[28]_i_1_n_5\,
      O(1) => \accumulator_reg[28]_i_1_n_6\,
      O(0) => \accumulator_reg[28]_i_1_n_7\,
      S(3) => \accumulator[28]_i_2_n_0\,
      S(2) => \accumulator[28]_i_3_n_0\,
      S(1) => \accumulator[28]_i_4_n_0\,
      S(0) => \accumulator[28]_i_5_n_0\
    );
\accumulator_reg[29]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \accumulator_reg[28]_i_1_n_6\,
      Q => accumulator_reg(29),
      R => reset
    );
\accumulator_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \accumulator_reg[0]_i_1_n_5\,
      Q => accumulator_reg(2),
      R => reset
    );
\accumulator_reg[30]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \accumulator_reg[28]_i_1_n_5\,
      Q => accumulator_reg(30),
      R => reset
    );
\accumulator_reg[31]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \accumulator_reg[28]_i_1_n_4\,
      Q => accumulator_reg(31),
      R => reset
    );
\accumulator_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \accumulator_reg[0]_i_1_n_4\,
      Q => accumulator_reg(3),
      R => reset
    );
\accumulator_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \accumulator_reg[4]_i_1_n_7\,
      Q => accumulator_reg(4),
      R => reset
    );
\accumulator_reg[4]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \accumulator_reg[0]_i_1_n_0\,
      CO(3) => \accumulator_reg[4]_i_1_n_0\,
      CO(2) => \accumulator_reg[4]_i_1_n_1\,
      CO(1) => \accumulator_reg[4]_i_1_n_2\,
      CO(0) => \accumulator_reg[4]_i_1_n_3\,
      CYINIT => '0',
      DI(3) => \ARG_carry__3_n_6\,
      DI(2) => \ARG_carry__3_n_7\,
      DI(1) => \ARG_carry__2_n_4\,
      DI(0) => \ARG_carry__2_n_5\,
      O(3) => \accumulator_reg[4]_i_1_n_4\,
      O(2) => \accumulator_reg[4]_i_1_n_5\,
      O(1) => \accumulator_reg[4]_i_1_n_6\,
      O(0) => \accumulator_reg[4]_i_1_n_7\,
      S(3) => \accumulator[4]_i_2_n_0\,
      S(2) => \accumulator[4]_i_3_n_0\,
      S(1) => \accumulator[4]_i_4_n_0\,
      S(0) => \accumulator[4]_i_5_n_0\
    );
\accumulator_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \accumulator_reg[4]_i_1_n_6\,
      Q => accumulator_reg(5),
      R => reset
    );
\accumulator_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \accumulator_reg[4]_i_1_n_5\,
      Q => accumulator_reg(6),
      R => reset
    );
\accumulator_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \accumulator_reg[4]_i_1_n_4\,
      Q => accumulator_reg(7),
      R => reset
    );
\accumulator_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \accumulator_reg[11]_i_1_n_7\,
      Q => accumulator_reg(8),
      R => reset
    );
\accumulator_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \accumulator_reg[11]_i_1_n_6\,
      Q => accumulator_reg(9),
      R => reset
    );
pulse_sync1_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => pulse_in,
      Q => pulse_sync1,
      R => reset
    );
pulse_sync2_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => pulse_sync1,
      Q => pulse_sync2,
      R => reset
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity FNPLL_filt_iir_0_0 is
  port (
    clk : in STD_LOGIC;
    reset : in STD_LOGIC;
    pulse_in : in STD_LOGIC;
    ctrl_out : out STD_LOGIC_VECTOR ( 15 downto 0 )
  );
  attribute NotValidForBitStream : boolean;
  attribute NotValidForBitStream of FNPLL_filt_iir_0_0 : entity is true;
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of FNPLL_filt_iir_0_0 : entity is "FNPLL_filt_iir_0_0,filt_iir,{}";
  attribute downgradeipidentifiedwarnings : string;
  attribute downgradeipidentifiedwarnings of FNPLL_filt_iir_0_0 : entity is "yes";
  attribute ip_definition_source : string;
  attribute ip_definition_source of FNPLL_filt_iir_0_0 : entity is "module_ref";
  attribute x_core_info : string;
  attribute x_core_info of FNPLL_filt_iir_0_0 : entity is "filt_iir,Vivado 2025.1";
end FNPLL_filt_iir_0_0;

architecture STRUCTURE of FNPLL_filt_iir_0_0 is
  attribute x_interface_info : string;
  attribute x_interface_info of clk : signal is "xilinx.com:signal:clock:1.0 clk CLK";
  attribute x_interface_mode : string;
  attribute x_interface_mode of clk : signal is "slave clk";
  attribute x_interface_parameter : string;
  attribute x_interface_parameter of clk : signal is "XIL_INTERFACENAME clk, ASSOCIATED_RESET reset, FREQ_HZ 300625000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, INSERT_VIP 0";
  attribute x_interface_info of reset : signal is "xilinx.com:signal:reset:1.0 reset RST";
  attribute x_interface_mode of reset : signal is "slave reset";
  attribute x_interface_parameter of reset : signal is "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
begin
U0: entity work.FNPLL_filt_iir_0_0_filt_iir
     port map (
      clk => clk,
      ctrl_out(15 downto 0) => ctrl_out(15 downto 0),
      pulse_in => pulse_in,
      reset => reset
    );
end STRUCTURE;
