// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2025.1 (win64) Build 6140274 Thu May 22 00:12:29 MDT 2025
// Date        : Thu Dec 18 17:28:27 2025
// Host        : LAPTOP-L3CRKKNJ running 64-bit major release  (build 9200)
// Command     : write_verilog -force -mode funcsim
//               c:/Vivado_Debug/FNPLL6/FNPLL2.gen/sources_1/bd/FNPLL/ip/FNPLL_pfd_sync_0_0/FNPLL_pfd_sync_0_0_sim_netlist.v
// Design      : FNPLL_pfd_sync_0_0
// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
//               or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device      : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

(* CHECK_LICENSE_TYPE = "FNPLL_pfd_sync_0_0,pfd_sync,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "module_ref" *) 
(* x_core_info = "pfd_sync,Vivado 2025.1" *) 
(* NotValidForBitStream *)
module FNPLL_pfd_sync_0_0
   (clk,
    rst_n,
    ref_in,
    fb_in,
    up,
    dn);
  (* x_interface_info = "xilinx.com:signal:clock:1.0 clk CLK" *) (* x_interface_mode = "slave clk" *) (* x_interface_parameter = "XIL_INTERFACENAME clk, FREQ_HZ 200416666, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, INSERT_VIP 0" *) input clk;
  (* x_interface_info = "xilinx.com:signal:reset:1.0 rst_n RST" *) (* x_interface_mode = "slave rst_n" *) (* x_interface_parameter = "XIL_INTERFACENAME rst_n, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input rst_n;
  input ref_in;
  input fb_in;
  output up;
  output dn;

  wire clk;
  wire dn;
  wire fb_in;
  wire ref_in;
  wire rst_n;
  wire up;

  FNPLL_pfd_sync_0_0_pfd_sync U0
       (.clk(clk),
        .dn(dn),
        .fb_in(fb_in),
        .ref_in(ref_in),
        .rst_n(rst_n),
        .up(up));
endmodule

(* ORIG_REF_NAME = "pfd_sync" *) 
module FNPLL_pfd_sync_0_0_pfd_sync
   (up,
    dn,
    rst_n,
    clk,
    fb_in,
    ref_in);
  output up;
  output dn;
  input rst_n;
  input clk;
  input fb_in;
  input ref_in;

  wire clk;
  wire dn;
  wire dn_q_i_1_n_0;
  wire fb_in;
  wire \fb_sync_reg_n_0_[1] ;
  wire [1:1]p_0_in;
  wire [1:1]p_0_in__0;
  wire ref_in;
  wire \ref_sync_reg_n_0_[1] ;
  wire rst_n;
  wire up;
  wire up_q_i_1_n_0;

  LUT5 #(
    .INIT(32'h00000F22)) 
    dn_q_i_1
       (.I0(\fb_sync_reg_n_0_[1] ),
        .I1(p_0_in),
        .I2(up),
        .I3(dn),
        .I4(rst_n),
        .O(dn_q_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    dn_q_reg
       (.C(clk),
        .CE(1'b1),
        .D(dn_q_i_1_n_0),
        .Q(dn),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \fb_sync_reg[0] 
       (.C(clk),
        .CE(1'b1),
        .D(fb_in),
        .Q(p_0_in),
        .R(rst_n));
  FDRE #(
    .INIT(1'b0)) 
    \fb_sync_reg[1] 
       (.C(clk),
        .CE(1'b1),
        .D(p_0_in),
        .Q(\fb_sync_reg_n_0_[1] ),
        .R(rst_n));
  FDRE #(
    .INIT(1'b0)) 
    \ref_sync_reg[0] 
       (.C(clk),
        .CE(1'b1),
        .D(ref_in),
        .Q(p_0_in__0),
        .R(rst_n));
  FDRE #(
    .INIT(1'b0)) 
    \ref_sync_reg[1] 
       (.C(clk),
        .CE(1'b1),
        .D(p_0_in__0),
        .Q(\ref_sync_reg_n_0_[1] ),
        .R(rst_n));
  LUT5 #(
    .INIT(32'h000002F2)) 
    up_q_i_1
       (.I0(\ref_sync_reg_n_0_[1] ),
        .I1(p_0_in__0),
        .I2(up),
        .I3(dn),
        .I4(rst_n),
        .O(up_q_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    up_q_reg
       (.C(clk),
        .CE(1'b1),
        .D(up_q_i_1_n_0),
        .Q(up),
        .R(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale  1 ps / 1 ps

module glbl ();

    parameter ROC_WIDTH = 100000;
    parameter TOC_WIDTH = 0;
    parameter GRES_WIDTH = 10000;
    parameter GRES_START = 10000;

//--------   STARTUP Globals --------------
    wire GSR;
    wire GTS;
    wire GWE;
    wire PRLD;
    wire GRESTORE;
    tri1 p_up_tmp;
    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;

    wire PROGB_GLBL;
    wire CCLKO_GLBL;
    wire FCSBO_GLBL;
    wire [3:0] DO_GLBL;
    wire [3:0] DI_GLBL;
   
    reg GSR_int;
    reg GTS_int;
    reg PRLD_int;
    reg GRESTORE_int;

//--------   JTAG Globals --------------
    wire JTAG_TDO_GLBL;
    wire JTAG_TCK_GLBL;
    wire JTAG_TDI_GLBL;
    wire JTAG_TMS_GLBL;
    wire JTAG_TRST_GLBL;

    reg JTAG_CAPTURE_GLBL;
    reg JTAG_RESET_GLBL;
    reg JTAG_SHIFT_GLBL;
    reg JTAG_UPDATE_GLBL;
    reg JTAG_RUNTEST_GLBL;

    reg JTAG_SEL1_GLBL = 0;
    reg JTAG_SEL2_GLBL = 0 ;
    reg JTAG_SEL3_GLBL = 0;
    reg JTAG_SEL4_GLBL = 0;

    reg JTAG_USER_TDO1_GLBL = 1'bz;
    reg JTAG_USER_TDO2_GLBL = 1'bz;
    reg JTAG_USER_TDO3_GLBL = 1'bz;
    reg JTAG_USER_TDO4_GLBL = 1'bz;

    assign (strong1, weak0) GSR = GSR_int;
    assign (strong1, weak0) GTS = GTS_int;
    assign (weak1, weak0) PRLD = PRLD_int;
    assign (strong1, weak0) GRESTORE = GRESTORE_int;

    initial begin
	GSR_int = 1'b1;
	PRLD_int = 1'b1;
	#(ROC_WIDTH)
	GSR_int = 1'b0;
	PRLD_int = 1'b0;
    end

    initial begin
	GTS_int = 1'b1;
	#(TOC_WIDTH)
	GTS_int = 1'b0;
    end

    initial begin 
	GRESTORE_int = 1'b0;
	#(GRES_START);
	GRESTORE_int = 1'b1;
	#(GRES_WIDTH);
	GRESTORE_int = 1'b0;
    end

endmodule
`endif
