-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2025.1 (win64) Build 6140274 Thu May 22 00:12:29 MDT 2025
-- Date        : Mon Dec 15 05:53:44 2025
-- Host        : LAPTOP-L3CRKKNJ running 64-bit major release  (build 9200)
-- Command     : write_vhdl -force -mode funcsim
--               c:/Vivado_Debug/FNPLL4/FNPLL2.gen/sources_1/bd/FNPLL/ip/FNPLL_uart_rx_tx_regs_0_0/FNPLL_uart_rx_tx_regs_0_0_sim_netlist.vhdl
-- Design      : FNPLL_uart_rx_tx_regs_0_0
-- Purpose     : This VHDL netlist is a functional simulation representation of the design and should not be modified or
--               synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device      : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity FNPLL_uart_rx_tx_regs_0_0_uart_rx_tx_regs is
  port (
    reg16_out : out STD_LOGIC_VECTOR ( 15 downto 0 );
    reg8_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
    tx : out STD_LOGIC;
    new_data : out STD_LOGIC;
    rst : in STD_LOGIC;
    clk : in STD_LOGIC;
    rx : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of FNPLL_uart_rx_tx_regs_0_0_uart_rx_tx_regs : entity is "uart_rx_tx_regs";
end FNPLL_uart_rx_tx_regs_0_0_uart_rx_tx_regs;

architecture STRUCTURE of FNPLL_uart_rx_tx_regs_0_0_uart_rx_tx_regs is
  signal \FSM_sequential_tx_state[0]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_state[0]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_tx_state[1]_i_1_n_0\ : STD_LOGIC;
  signal data_pulse_i_1_n_0 : STD_LOGIC;
  signal p_0_in : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \reg16[15]_i_1_n_0\ : STD_LOGIC;
  signal \reg16[7]_i_1_n_0\ : STD_LOGIC;
  signal \reg8[7]_i_1_n_0\ : STD_LOGIC;
  signal \reg8[7]_i_2_n_0\ : STD_LOGIC;
  signal \reg8[7]_i_3_n_0\ : STD_LOGIC;
  signal \^reg8_out\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal rx_active_i_1_n_0 : STD_LOGIC;
  signal rx_active_reg_n_0 : STD_LOGIC;
  signal rx_baud_cnt : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal \rx_baud_cnt[4]_i_2_n_0\ : STD_LOGIC;
  signal \rx_baud_cnt[5]_i_2_n_0\ : STD_LOGIC;
  signal \rx_baud_cnt[9]_i_1_n_0\ : STD_LOGIC;
  signal \rx_baud_cnt[9]_i_2_n_0\ : STD_LOGIC;
  signal \rx_baud_cnt[9]_i_4_n_0\ : STD_LOGIC;
  signal rx_baud_cnt_0 : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal \rx_bit_cnt[0]_i_1_n_0\ : STD_LOGIC;
  signal \rx_bit_cnt[3]_i_1_n_0\ : STD_LOGIC;
  signal \rx_bit_cnt[3]_i_2_n_0\ : STD_LOGIC;
  signal rx_bit_cnt_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \rx_idx[0]_i_1_n_0\ : STD_LOGIC;
  signal \rx_idx[1]_i_1_n_0\ : STD_LOGIC;
  signal \rx_idx_reg_n_0_[0]\ : STD_LOGIC;
  signal \rx_idx_reg_n_0_[1]\ : STD_LOGIC;
  signal rx_meta : STD_LOGIC;
  signal rx_shift : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \rx_shift[0]_i_1_n_0\ : STD_LOGIC;
  signal \rx_shift[1]_i_1_n_0\ : STD_LOGIC;
  signal \rx_shift[1]_i_2_n_0\ : STD_LOGIC;
  signal \rx_shift[2]_i_1_n_0\ : STD_LOGIC;
  signal \rx_shift[3]_i_1_n_0\ : STD_LOGIC;
  signal \rx_shift[3]_i_2_n_0\ : STD_LOGIC;
  signal \rx_shift[4]_i_1_n_0\ : STD_LOGIC;
  signal \rx_shift[5]_i_1_n_0\ : STD_LOGIC;
  signal \rx_shift[5]_i_2_n_0\ : STD_LOGIC;
  signal \rx_shift[6]_i_1_n_0\ : STD_LOGIC;
  signal \rx_shift[6]_i_2_n_0\ : STD_LOGIC;
  signal \rx_shift[6]_i_3_n_0\ : STD_LOGIC;
  signal \rx_shift[7]_i_1_n_0\ : STD_LOGIC;
  signal \rx_shift[7]_i_2_n_0\ : STD_LOGIC;
  signal rx_sync : STD_LOGIC;
  signal \^tx\ : STD_LOGIC;
  signal tx_baud_cnt : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal \tx_baud_cnt[3]_i_2_n_0\ : STD_LOGIC;
  signal \tx_baud_cnt[3]_i_3_n_0\ : STD_LOGIC;
  signal \tx_baud_cnt[4]_i_2_n_0\ : STD_LOGIC;
  signal \tx_baud_cnt[4]_i_3_n_0\ : STD_LOGIC;
  signal \tx_baud_cnt[6]_i_2_n_0\ : STD_LOGIC;
  signal \tx_baud_cnt[6]_i_3_n_0\ : STD_LOGIC;
  signal \tx_baud_cnt[9]_i_1_n_0\ : STD_LOGIC;
  signal \tx_baud_cnt[9]_i_3_n_0\ : STD_LOGIC;
  signal \tx_baud_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \tx_baud_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \tx_baud_cnt_reg_n_0_[2]\ : STD_LOGIC;
  signal \tx_baud_cnt_reg_n_0_[3]\ : STD_LOGIC;
  signal \tx_baud_cnt_reg_n_0_[4]\ : STD_LOGIC;
  signal \tx_baud_cnt_reg_n_0_[5]\ : STD_LOGIC;
  signal \tx_baud_cnt_reg_n_0_[6]\ : STD_LOGIC;
  signal \tx_baud_cnt_reg_n_0_[7]\ : STD_LOGIC;
  signal \tx_baud_cnt_reg_n_0_[8]\ : STD_LOGIC;
  signal \tx_baud_cnt_reg_n_0_[9]\ : STD_LOGIC;
  signal \tx_bit_cnt[0]_i_1_n_0\ : STD_LOGIC;
  signal \tx_bit_cnt[1]_i_1_n_0\ : STD_LOGIC;
  signal \tx_bit_cnt[1]_i_2_n_0\ : STD_LOGIC;
  signal \tx_bit_cnt[1]_i_3_n_0\ : STD_LOGIC;
  signal \tx_bit_cnt[1]_i_4_n_0\ : STD_LOGIC;
  signal \tx_bit_cnt[1]_i_5_n_0\ : STD_LOGIC;
  signal \tx_bit_cnt[2]_i_1_n_0\ : STD_LOGIC;
  signal \tx_bit_cnt[2]_i_2_n_0\ : STD_LOGIC;
  signal \tx_bit_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \tx_bit_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \tx_bit_cnt_reg_n_0_[2]\ : STD_LOGIC;
  signal \tx_idx[0]_i_1_n_0\ : STD_LOGIC;
  signal \tx_idx[1]_i_1_n_0\ : STD_LOGIC;
  signal \tx_idx_reg_n_0_[0]\ : STD_LOGIC;
  signal \tx_idx_reg_n_0_[1]\ : STD_LOGIC;
  signal tx_reg_i_1_n_0 : STD_LOGIC;
  signal tx_reg_i_2_n_0 : STD_LOGIC;
  signal tx_reg_i_3_n_0 : STD_LOGIC;
  signal tx_reg_i_4_n_0 : STD_LOGIC;
  signal tx_reg_i_5_n_0 : STD_LOGIC;
  signal tx_reg_i_6_n_0 : STD_LOGIC;
  signal tx_reg_i_7_n_0 : STD_LOGIC;
  signal tx_reg_i_8_n_0 : STD_LOGIC;
  signal \tx_shift[7]_i_1_n_0\ : STD_LOGIC;
  signal \tx_shift[7]_i_2_n_0\ : STD_LOGIC;
  signal \tx_shift_reg_n_0_[0]\ : STD_LOGIC;
  signal \tx_shift_reg_n_0_[1]\ : STD_LOGIC;
  signal \tx_shift_reg_n_0_[2]\ : STD_LOGIC;
  signal \tx_shift_reg_n_0_[3]\ : STD_LOGIC;
  signal \tx_shift_reg_n_0_[4]\ : STD_LOGIC;
  signal \tx_shift_reg_n_0_[5]\ : STD_LOGIC;
  signal \tx_shift_reg_n_0_[6]\ : STD_LOGIC;
  signal \tx_shift_reg_n_0_[7]\ : STD_LOGIC;
  signal \tx_state__0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_sequential_tx_state[0]_i_2\ : label is "soft_lutpair8";
  attribute SOFT_HLUTNM of \FSM_sequential_tx_state[1]_i_1\ : label is "soft_lutpair10";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_sequential_tx_state_reg[0]\ : label is "tx_data:10,tx_stop:11,tx_start:01,tx_idle:00";
  attribute FSM_ENCODED_STATES of \FSM_sequential_tx_state_reg[1]\ : label is "tx_data:10,tx_stop:11,tx_start:01,tx_idle:00";
  attribute SOFT_HLUTNM of data_pulse_i_1 : label is "soft_lutpair11";
  attribute SOFT_HLUTNM of \reg8[7]_i_2\ : label is "soft_lutpair6";
  attribute SOFT_HLUTNM of \reg8[7]_i_3\ : label is "soft_lutpair5";
  attribute SOFT_HLUTNM of rx_active_i_1 : label is "soft_lutpair15";
  attribute SOFT_HLUTNM of \rx_baud_cnt[0]_i_1\ : label is "soft_lutpair19";
  attribute SOFT_HLUTNM of \rx_baud_cnt[1]_i_1\ : label is "soft_lutpair19";
  attribute SOFT_HLUTNM of \rx_baud_cnt[2]_i_1\ : label is "soft_lutpair7";
  attribute SOFT_HLUTNM of \rx_baud_cnt[5]_i_2\ : label is "soft_lutpair7";
  attribute SOFT_HLUTNM of \rx_baud_cnt[6]_i_1\ : label is "soft_lutpair4";
  attribute SOFT_HLUTNM of \rx_baud_cnt[7]_i_1\ : label is "soft_lutpair4";
  attribute SOFT_HLUTNM of \rx_baud_cnt[8]_i_1\ : label is "soft_lutpair5";
  attribute SOFT_HLUTNM of \rx_bit_cnt[0]_i_1\ : label is "soft_lutpair20";
  attribute SOFT_HLUTNM of \rx_bit_cnt[1]_i_1\ : label is "soft_lutpair20";
  attribute SOFT_HLUTNM of \rx_bit_cnt[2]_i_1\ : label is "soft_lutpair12";
  attribute SOFT_HLUTNM of \rx_bit_cnt[3]_i_3\ : label is "soft_lutpair12";
  attribute SOFT_HLUTNM of \rx_idx[0]_i_1\ : label is "soft_lutpair16";
  attribute SOFT_HLUTNM of \rx_idx[1]_i_1\ : label is "soft_lutpair16";
  attribute SOFT_HLUTNM of \rx_shift[1]_i_2\ : label is "soft_lutpair13";
  attribute SOFT_HLUTNM of \rx_shift[3]_i_2\ : label is "soft_lutpair13";
  attribute SOFT_HLUTNM of \rx_shift[5]_i_2\ : label is "soft_lutpair14";
  attribute SOFT_HLUTNM of \rx_shift[6]_i_2\ : label is "soft_lutpair15";
  attribute SOFT_HLUTNM of \rx_shift[6]_i_3\ : label is "soft_lutpair6";
  attribute SOFT_HLUTNM of \rx_shift[7]_i_2\ : label is "soft_lutpair14";
  attribute SOFT_HLUTNM of \tx_baud_cnt[0]_i_1\ : label is "soft_lutpair17";
  attribute SOFT_HLUTNM of \tx_baud_cnt[1]_i_1\ : label is "soft_lutpair1";
  attribute SOFT_HLUTNM of \tx_baud_cnt[2]_i_1\ : label is "soft_lutpair1";
  attribute SOFT_HLUTNM of \tx_baud_cnt[3]_i_2\ : label is "soft_lutpair2";
  attribute SOFT_HLUTNM of \tx_baud_cnt[4]_i_2\ : label is "soft_lutpair3";
  attribute SOFT_HLUTNM of \tx_baud_cnt[4]_i_3\ : label is "soft_lutpair17";
  attribute SOFT_HLUTNM of \tx_baud_cnt[6]_i_2\ : label is "soft_lutpair3";
  attribute SOFT_HLUTNM of \tx_baud_cnt[6]_i_3\ : label is "soft_lutpair2";
  attribute SOFT_HLUTNM of \tx_baud_cnt[9]_i_3\ : label is "soft_lutpair18";
  attribute SOFT_HLUTNM of \tx_bit_cnt[1]_i_1\ : label is "soft_lutpair9";
  attribute SOFT_HLUTNM of \tx_bit_cnt[1]_i_4\ : label is "soft_lutpair18";
  attribute SOFT_HLUTNM of \tx_bit_cnt[1]_i_5\ : label is "soft_lutpair11";
  attribute SOFT_HLUTNM of \tx_bit_cnt[2]_i_2\ : label is "soft_lutpair9";
  attribute SOFT_HLUTNM of \tx_idx[0]_i_1\ : label is "soft_lutpair0";
  attribute SOFT_HLUTNM of \tx_idx[1]_i_1\ : label is "soft_lutpair0";
  attribute SOFT_HLUTNM of tx_reg_i_4 : label is "soft_lutpair10";
  attribute SOFT_HLUTNM of tx_reg_i_8 : label is "soft_lutpair8";
begin
  reg8_out(7 downto 0) <= \^reg8_out\(7 downto 0);
  tx <= \^tx\;
\FSM_sequential_tx_state[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B0B000F0FFFF0000"
    )
        port map (
      I0 => \tx_idx_reg_n_0_[0]\,
      I1 => \tx_idx_reg_n_0_[1]\,
      I2 => \tx_state__0\(1),
      I3 => \FSM_sequential_tx_state[0]_i_2_n_0\,
      I4 => \tx_state__0\(0),
      I5 => tx_reg_i_5_n_0,
      O => \FSM_sequential_tx_state[0]_i_1_n_0\
    );
\FSM_sequential_tx_state[0]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"7F"
    )
        port map (
      I0 => \tx_bit_cnt_reg_n_0_[1]\,
      I1 => \tx_bit_cnt_reg_n_0_[0]\,
      I2 => \tx_bit_cnt_reg_n_0_[2]\,
      O => \FSM_sequential_tx_state[0]_i_2_n_0\
    );
\FSM_sequential_tx_state[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => \tx_state__0\(1),
      I1 => \tx_state__0\(0),
      I2 => tx_reg_i_5_n_0,
      O => \FSM_sequential_tx_state[1]_i_1_n_0\
    );
\FSM_sequential_tx_state_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \FSM_sequential_tx_state[0]_i_1_n_0\,
      Q => \tx_state__0\(0),
      R => rst
    );
\FSM_sequential_tx_state_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \FSM_sequential_tx_state[1]_i_1_n_0\,
      Q => \tx_state__0\(1),
      R => rst
    );
data_pulse_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0400"
    )
        port map (
      I0 => \rx_idx_reg_n_0_[0]\,
      I1 => \rx_idx_reg_n_0_[1]\,
      I2 => rst,
      I3 => \reg8[7]_i_2_n_0\,
      O => data_pulse_i_1_n_0
    );
data_pulse_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => data_pulse_i_1_n_0,
      Q => new_data,
      R => '0'
    );
\reg16[15]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \rx_idx_reg_n_0_[0]\,
      I1 => \rx_idx_reg_n_0_[1]\,
      I2 => \reg8[7]_i_2_n_0\,
      O => \reg16[15]_i_1_n_0\
    );
\reg16[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \rx_idx_reg_n_0_[1]\,
      I1 => \rx_idx_reg_n_0_[0]\,
      I2 => \reg8[7]_i_2_n_0\,
      O => \reg16[7]_i_1_n_0\
    );
\reg16_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \reg16[7]_i_1_n_0\,
      D => rx_shift(0),
      Q => reg16_out(0),
      R => rst
    );
\reg16_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \reg16[15]_i_1_n_0\,
      D => rx_shift(2),
      Q => reg16_out(10),
      R => rst
    );
\reg16_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \reg16[15]_i_1_n_0\,
      D => rx_shift(3),
      Q => reg16_out(11),
      R => rst
    );
\reg16_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \reg16[15]_i_1_n_0\,
      D => rx_shift(4),
      Q => reg16_out(12),
      R => rst
    );
\reg16_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \reg16[15]_i_1_n_0\,
      D => rx_shift(5),
      Q => reg16_out(13),
      R => rst
    );
\reg16_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \reg16[15]_i_1_n_0\,
      D => rx_shift(6),
      Q => reg16_out(14),
      R => rst
    );
\reg16_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \reg16[15]_i_1_n_0\,
      D => rx_shift(7),
      Q => reg16_out(15),
      R => rst
    );
\reg16_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \reg16[7]_i_1_n_0\,
      D => rx_shift(1),
      Q => reg16_out(1),
      R => rst
    );
\reg16_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \reg16[7]_i_1_n_0\,
      D => rx_shift(2),
      Q => reg16_out(2),
      R => rst
    );
\reg16_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \reg16[7]_i_1_n_0\,
      D => rx_shift(3),
      Q => reg16_out(3),
      R => rst
    );
\reg16_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \reg16[7]_i_1_n_0\,
      D => rx_shift(4),
      Q => reg16_out(4),
      R => rst
    );
\reg16_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \reg16[7]_i_1_n_0\,
      D => rx_shift(5),
      Q => reg16_out(5),
      R => rst
    );
\reg16_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \reg16[7]_i_1_n_0\,
      D => rx_shift(6),
      Q => reg16_out(6),
      R => rst
    );
\reg16_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \reg16[7]_i_1_n_0\,
      D => rx_shift(7),
      Q => reg16_out(7),
      R => rst
    );
\reg16_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \reg16[15]_i_1_n_0\,
      D => rx_shift(0),
      Q => reg16_out(8),
      R => rst
    );
\reg16_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \reg16[15]_i_1_n_0\,
      D => rx_shift(1),
      Q => reg16_out(9),
      R => rst
    );
\reg8[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \rx_idx_reg_n_0_[1]\,
      I1 => \rx_idx_reg_n_0_[0]\,
      I2 => \reg8[7]_i_2_n_0\,
      O => \reg8[7]_i_1_n_0\
    );
\reg8[7]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00080000"
    )
        port map (
      I0 => \rx_shift[7]_i_2_n_0\,
      I1 => rx_bit_cnt_reg(0),
      I2 => \rx_baud_cnt[9]_i_4_n_0\,
      I3 => \reg8[7]_i_3_n_0\,
      I4 => rx_active_reg_n_0,
      O => \reg8[7]_i_2_n_0\
    );
\reg8[7]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => rx_baud_cnt(7),
      I1 => rx_baud_cnt(6),
      I2 => rx_baud_cnt(9),
      I3 => rx_baud_cnt(8),
      O => \reg8[7]_i_3_n_0\
    );
\reg8_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \reg8[7]_i_1_n_0\,
      D => rx_shift(0),
      Q => \^reg8_out\(0),
      R => rst
    );
\reg8_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \reg8[7]_i_1_n_0\,
      D => rx_shift(1),
      Q => \^reg8_out\(1),
      R => rst
    );
\reg8_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \reg8[7]_i_1_n_0\,
      D => rx_shift(2),
      Q => \^reg8_out\(2),
      R => rst
    );
\reg8_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \reg8[7]_i_1_n_0\,
      D => rx_shift(3),
      Q => \^reg8_out\(3),
      R => rst
    );
\reg8_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \reg8[7]_i_1_n_0\,
      D => rx_shift(4),
      Q => \^reg8_out\(4),
      R => rst
    );
\reg8_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \reg8[7]_i_1_n_0\,
      D => rx_shift(5),
      Q => \^reg8_out\(5),
      R => rst
    );
\reg8_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \reg8[7]_i_1_n_0\,
      D => rx_shift(6),
      Q => \^reg8_out\(6),
      R => rst
    );
\reg8_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \reg8[7]_i_1_n_0\,
      D => rx_shift(7),
      Q => \^reg8_out\(7),
      R => rst
    );
rx_active_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"005B"
    )
        port map (
      I0 => rx_active_reg_n_0,
      I1 => rx_sync,
      I2 => \reg8[7]_i_2_n_0\,
      I3 => rst,
      O => rx_active_i_1_n_0
    );
rx_active_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => rx_active_i_1_n_0,
      Q => rx_active_reg_n_0,
      R => '0'
    );
\rx_baud_cnt[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => rx_baud_cnt(0),
      O => rx_baud_cnt_0(0)
    );
\rx_baud_cnt[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => rx_baud_cnt(1),
      I1 => rx_baud_cnt(0),
      O => rx_baud_cnt_0(1)
    );
\rx_baud_cnt[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A9"
    )
        port map (
      I0 => rx_baud_cnt(2),
      I1 => rx_baud_cnt(0),
      I2 => rx_baud_cnt(1),
      O => rx_baud_cnt_0(2)
    );
\rx_baud_cnt[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0F0F0F0F0F0F00E"
    )
        port map (
      I0 => \rx_baud_cnt[4]_i_2_n_0\,
      I1 => rx_baud_cnt(4),
      I2 => rx_baud_cnt(3),
      I3 => rx_baud_cnt(1),
      I4 => rx_baud_cnt(0),
      I5 => rx_baud_cnt(2),
      O => rx_baud_cnt_0(3)
    );
\rx_baud_cnt[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFE0001FFFE0000"
    )
        port map (
      I0 => rx_baud_cnt(3),
      I1 => rx_baud_cnt(1),
      I2 => rx_baud_cnt(0),
      I3 => rx_baud_cnt(2),
      I4 => rx_baud_cnt(4),
      I5 => \rx_baud_cnt[4]_i_2_n_0\,
      O => rx_baud_cnt_0(4)
    );
\rx_baud_cnt[4]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => rx_baud_cnt(8),
      I1 => rx_baud_cnt(9),
      I2 => rx_baud_cnt(6),
      I3 => rx_baud_cnt(7),
      I4 => rx_baud_cnt(5),
      O => \rx_baud_cnt[4]_i_2_n_0\
    );
\rx_baud_cnt[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9999999999999998"
    )
        port map (
      I0 => \rx_baud_cnt[5]_i_2_n_0\,
      I1 => rx_baud_cnt(5),
      I2 => rx_baud_cnt(7),
      I3 => rx_baud_cnt(6),
      I4 => rx_baud_cnt(9),
      I5 => rx_baud_cnt(8),
      O => rx_baud_cnt_0(5)
    );
\rx_baud_cnt[5]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => rx_baud_cnt(3),
      I1 => rx_baud_cnt(1),
      I2 => rx_baud_cnt(0),
      I3 => rx_baud_cnt(2),
      I4 => rx_baud_cnt(4),
      O => \rx_baud_cnt[5]_i_2_n_0\
    );
\rx_baud_cnt[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF0000FE"
    )
        port map (
      I0 => rx_baud_cnt(9),
      I1 => rx_baud_cnt(8),
      I2 => rx_baud_cnt(7),
      I3 => rx_baud_cnt(6),
      I4 => \rx_baud_cnt[9]_i_4_n_0\,
      O => rx_baud_cnt_0(6)
    );
\rx_baud_cnt[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A9A9A9A8"
    )
        port map (
      I0 => rx_baud_cnt(7),
      I1 => rx_baud_cnt(6),
      I2 => \rx_baud_cnt[9]_i_4_n_0\,
      I3 => rx_baud_cnt(8),
      I4 => rx_baud_cnt(9),
      O => rx_baud_cnt_0(7)
    );
\rx_baud_cnt[8]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FE01FE00"
    )
        port map (
      I0 => \rx_baud_cnt[9]_i_4_n_0\,
      I1 => rx_baud_cnt(6),
      I2 => rx_baud_cnt(7),
      I3 => rx_baud_cnt(8),
      I4 => rx_baud_cnt(9),
      O => rx_baud_cnt_0(8)
    );
\rx_baud_cnt[9]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => rx_active_reg_n_0,
      I1 => rst,
      I2 => rx_sync,
      O => \rx_baud_cnt[9]_i_1_n_0\
    );
\rx_baud_cnt[9]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => rx_active_reg_n_0,
      I1 => rst,
      O => \rx_baud_cnt[9]_i_2_n_0\
    );
\rx_baud_cnt[9]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF00FE01"
    )
        port map (
      I0 => \rx_baud_cnt[9]_i_4_n_0\,
      I1 => rx_baud_cnt(7),
      I2 => rx_baud_cnt(6),
      I3 => rx_baud_cnt(9),
      I4 => rx_baud_cnt(8),
      O => rx_baud_cnt_0(9)
    );
\rx_baud_cnt[9]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => rx_baud_cnt(4),
      I1 => rx_baud_cnt(2),
      I2 => rx_baud_cnt(0),
      I3 => rx_baud_cnt(1),
      I4 => rx_baud_cnt(3),
      I5 => rx_baud_cnt(5),
      O => \rx_baud_cnt[9]_i_4_n_0\
    );
\rx_baud_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \rx_baud_cnt[9]_i_2_n_0\,
      D => rx_baud_cnt_0(0),
      Q => rx_baud_cnt(0),
      R => \rx_baud_cnt[9]_i_1_n_0\
    );
\rx_baud_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \rx_baud_cnt[9]_i_2_n_0\,
      D => rx_baud_cnt_0(1),
      Q => rx_baud_cnt(1),
      R => \rx_baud_cnt[9]_i_1_n_0\
    );
\rx_baud_cnt_reg[2]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \rx_baud_cnt[9]_i_2_n_0\,
      D => rx_baud_cnt_0(2),
      Q => rx_baud_cnt(2),
      S => \rx_baud_cnt[9]_i_1_n_0\
    );
\rx_baud_cnt_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \rx_baud_cnt[9]_i_2_n_0\,
      D => rx_baud_cnt_0(3),
      Q => rx_baud_cnt(3),
      R => \rx_baud_cnt[9]_i_1_n_0\
    );
\rx_baud_cnt_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \rx_baud_cnt[9]_i_2_n_0\,
      D => rx_baud_cnt_0(4),
      Q => rx_baud_cnt(4),
      R => \rx_baud_cnt[9]_i_1_n_0\
    );
\rx_baud_cnt_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \rx_baud_cnt[9]_i_2_n_0\,
      D => rx_baud_cnt_0(5),
      Q => rx_baud_cnt(5),
      R => \rx_baud_cnt[9]_i_1_n_0\
    );
\rx_baud_cnt_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \rx_baud_cnt[9]_i_2_n_0\,
      D => rx_baud_cnt_0(6),
      Q => rx_baud_cnt(6),
      R => \rx_baud_cnt[9]_i_1_n_0\
    );
\rx_baud_cnt_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \rx_baud_cnt[9]_i_2_n_0\,
      D => rx_baud_cnt_0(7),
      Q => rx_baud_cnt(7),
      R => \rx_baud_cnt[9]_i_1_n_0\
    );
\rx_baud_cnt_reg[8]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \rx_baud_cnt[9]_i_2_n_0\,
      D => rx_baud_cnt_0(8),
      Q => rx_baud_cnt(8),
      S => \rx_baud_cnt[9]_i_1_n_0\
    );
\rx_baud_cnt_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \rx_baud_cnt[9]_i_2_n_0\,
      D => rx_baud_cnt_0(9),
      Q => rx_baud_cnt(9),
      R => \rx_baud_cnt[9]_i_1_n_0\
    );
\rx_bit_cnt[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => rx_bit_cnt_reg(0),
      O => \rx_bit_cnt[0]_i_1_n_0\
    );
\rx_bit_cnt[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => rx_bit_cnt_reg(0),
      I1 => rx_bit_cnt_reg(1),
      O => p_0_in(1)
    );
\rx_bit_cnt[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => rx_bit_cnt_reg(1),
      I1 => rx_bit_cnt_reg(0),
      I2 => rx_bit_cnt_reg(2),
      O => p_0_in(2)
    );
\rx_bit_cnt[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F1"
    )
        port map (
      I0 => rx_active_reg_n_0,
      I1 => rx_sync,
      I2 => rst,
      O => \rx_bit_cnt[3]_i_1_n_0\
    );
\rx_bit_cnt[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000100000000"
    )
        port map (
      I0 => \rx_baud_cnt[9]_i_4_n_0\,
      I1 => rx_baud_cnt(7),
      I2 => rx_baud_cnt(6),
      I3 => rx_baud_cnt(9),
      I4 => rx_baud_cnt(8),
      I5 => rx_active_reg_n_0,
      O => \rx_bit_cnt[3]_i_2_n_0\
    );
\rx_bit_cnt[3]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => rx_bit_cnt_reg(2),
      I1 => rx_bit_cnt_reg(0),
      I2 => rx_bit_cnt_reg(1),
      I3 => rx_bit_cnt_reg(3),
      O => p_0_in(3)
    );
\rx_bit_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \rx_bit_cnt[3]_i_2_n_0\,
      D => \rx_bit_cnt[0]_i_1_n_0\,
      Q => rx_bit_cnt_reg(0),
      R => \rx_bit_cnt[3]_i_1_n_0\
    );
\rx_bit_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \rx_bit_cnt[3]_i_2_n_0\,
      D => p_0_in(1),
      Q => rx_bit_cnt_reg(1),
      R => \rx_bit_cnt[3]_i_1_n_0\
    );
\rx_bit_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \rx_bit_cnt[3]_i_2_n_0\,
      D => p_0_in(2),
      Q => rx_bit_cnt_reg(2),
      R => \rx_bit_cnt[3]_i_1_n_0\
    );
\rx_bit_cnt_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \rx_bit_cnt[3]_i_2_n_0\,
      D => p_0_in(3),
      Q => rx_bit_cnt_reg(3),
      R => \rx_bit_cnt[3]_i_1_n_0\
    );
\rx_idx[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"34"
    )
        port map (
      I0 => \rx_idx_reg_n_0_[1]\,
      I1 => \reg8[7]_i_2_n_0\,
      I2 => \rx_idx_reg_n_0_[0]\,
      O => \rx_idx[0]_i_1_n_0\
    );
\rx_idx[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"38"
    )
        port map (
      I0 => \rx_idx_reg_n_0_[0]\,
      I1 => \reg8[7]_i_2_n_0\,
      I2 => \rx_idx_reg_n_0_[1]\,
      O => \rx_idx[1]_i_1_n_0\
    );
\rx_idx_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \rx_idx[0]_i_1_n_0\,
      Q => \rx_idx_reg_n_0_[0]\,
      R => rst
    );
\rx_idx_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \rx_idx[1]_i_1_n_0\,
      Q => \rx_idx_reg_n_0_[1]\,
      R => rst
    );
rx_meta_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => clk,
      CE => '1',
      D => rx,
      Q => rx_meta,
      R => '0'
    );
\rx_shift[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FEFFFFFF02000000"
    )
        port map (
      I0 => rx_sync,
      I1 => rx_bit_cnt_reg(1),
      I2 => rx_bit_cnt_reg(2),
      I3 => \rx_shift[6]_i_2_n_0\,
      I4 => \rx_shift[6]_i_3_n_0\,
      I5 => rx_shift(0),
      O => \rx_shift[0]_i_1_n_0\
    );
\rx_shift[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FBFF0800"
    )
        port map (
      I0 => rx_sync,
      I1 => \rx_shift[1]_i_2_n_0\,
      I2 => rx_bit_cnt_reg(0),
      I3 => \rx_bit_cnt[3]_i_2_n_0\,
      I4 => rx_shift(1),
      O => \rx_shift[1]_i_1_n_0\
    );
\rx_shift[1]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0002"
    )
        port map (
      I0 => rx_bit_cnt_reg(1),
      I1 => rx_bit_cnt_reg(3),
      I2 => rst,
      I3 => rx_bit_cnt_reg(2),
      O => \rx_shift[1]_i_2_n_0\
    );
\rx_shift[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EFFFFFFF20000000"
    )
        port map (
      I0 => rx_sync,
      I1 => rx_bit_cnt_reg(2),
      I2 => \rx_shift[6]_i_2_n_0\,
      I3 => rx_bit_cnt_reg(1),
      I4 => \rx_shift[6]_i_3_n_0\,
      I5 => rx_shift(2),
      O => \rx_shift[2]_i_1_n_0\
    );
\rx_shift[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FBFF0800"
    )
        port map (
      I0 => rx_sync,
      I1 => \rx_shift[3]_i_2_n_0\,
      I2 => rx_bit_cnt_reg(0),
      I3 => \rx_bit_cnt[3]_i_2_n_0\,
      I4 => rx_shift(3),
      O => \rx_shift[3]_i_1_n_0\
    );
\rx_shift[3]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0004"
    )
        port map (
      I0 => rx_bit_cnt_reg(1),
      I1 => rx_bit_cnt_reg(2),
      I2 => rst,
      I3 => rx_bit_cnt_reg(3),
      O => \rx_shift[3]_i_2_n_0\
    );
\rx_shift[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFBFFFFF00800000"
    )
        port map (
      I0 => rx_sync,
      I1 => \rx_shift[6]_i_2_n_0\,
      I2 => rx_bit_cnt_reg(2),
      I3 => rx_bit_cnt_reg(1),
      I4 => \rx_shift[6]_i_3_n_0\,
      I5 => rx_shift(4),
      O => \rx_shift[4]_i_1_n_0\
    );
\rx_shift[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FBFF0800"
    )
        port map (
      I0 => rx_sync,
      I1 => \rx_shift[5]_i_2_n_0\,
      I2 => rx_bit_cnt_reg(0),
      I3 => \rx_bit_cnt[3]_i_2_n_0\,
      I4 => rx_shift(5),
      O => \rx_shift[5]_i_1_n_0\
    );
\rx_shift[5]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0200"
    )
        port map (
      I0 => rx_bit_cnt_reg(1),
      I1 => rx_bit_cnt_reg(3),
      I2 => rst,
      I3 => rx_bit_cnt_reg(2),
      O => \rx_shift[5]_i_2_n_0\
    );
\rx_shift[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BFFFFFFF80000000"
    )
        port map (
      I0 => rx_sync,
      I1 => rx_bit_cnt_reg(2),
      I2 => \rx_shift[6]_i_2_n_0\,
      I3 => rx_bit_cnt_reg(1),
      I4 => \rx_shift[6]_i_3_n_0\,
      I5 => rx_shift(6),
      O => \rx_shift[6]_i_1_n_0\
    );
\rx_shift[6]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => rx_bit_cnt_reg(3),
      I1 => rst,
      O => \rx_shift[6]_i_2_n_0\
    );
\rx_shift[6]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0200"
    )
        port map (
      I0 => rx_active_reg_n_0,
      I1 => \reg8[7]_i_3_n_0\,
      I2 => \rx_baud_cnt[9]_i_4_n_0\,
      I3 => rx_bit_cnt_reg(0),
      O => \rx_shift[6]_i_3_n_0\
    );
\rx_shift[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFEFFFFF00200000"
    )
        port map (
      I0 => rx_sync,
      I1 => rst,
      I2 => \rx_shift[7]_i_2_n_0\,
      I3 => rx_bit_cnt_reg(0),
      I4 => \rx_bit_cnt[3]_i_2_n_0\,
      I5 => rx_shift(7),
      O => \rx_shift[7]_i_1_n_0\
    );
\rx_shift[7]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => rx_bit_cnt_reg(2),
      I1 => rx_bit_cnt_reg(1),
      I2 => rx_bit_cnt_reg(3),
      O => \rx_shift[7]_i_2_n_0\
    );
\rx_shift_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \rx_shift[0]_i_1_n_0\,
      Q => rx_shift(0),
      R => '0'
    );
\rx_shift_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \rx_shift[1]_i_1_n_0\,
      Q => rx_shift(1),
      R => '0'
    );
\rx_shift_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \rx_shift[2]_i_1_n_0\,
      Q => rx_shift(2),
      R => '0'
    );
\rx_shift_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \rx_shift[3]_i_1_n_0\,
      Q => rx_shift(3),
      R => '0'
    );
\rx_shift_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \rx_shift[4]_i_1_n_0\,
      Q => rx_shift(4),
      R => '0'
    );
\rx_shift_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \rx_shift[5]_i_1_n_0\,
      Q => rx_shift(5),
      R => '0'
    );
\rx_shift_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \rx_shift[6]_i_1_n_0\,
      Q => rx_shift(6),
      R => '0'
    );
\rx_shift_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \rx_shift[7]_i_1_n_0\,
      Q => rx_shift(7),
      R => '0'
    );
rx_sync_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => clk,
      CE => '1',
      D => rx_meta,
      Q => rx_sync,
      R => '0'
    );
\tx_baud_cnt[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"1F"
    )
        port map (
      I0 => \tx_state__0\(1),
      I1 => \tx_state__0\(0),
      I2 => \tx_baud_cnt_reg_n_0_[0]\,
      O => tx_baud_cnt(0)
    );
\tx_baud_cnt[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F11F"
    )
        port map (
      I0 => \tx_state__0\(0),
      I1 => \tx_state__0\(1),
      I2 => \tx_baud_cnt_reg_n_0_[1]\,
      I3 => \tx_baud_cnt_reg_n_0_[0]\,
      O => tx_baud_cnt(1)
    );
\tx_baud_cnt[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F1F1F11F"
    )
        port map (
      I0 => \tx_state__0\(0),
      I1 => \tx_state__0\(1),
      I2 => \tx_baud_cnt_reg_n_0_[2]\,
      I3 => \tx_baud_cnt_reg_n_0_[0]\,
      I4 => \tx_baud_cnt_reg_n_0_[1]\,
      O => tx_baud_cnt(2)
    );
\tx_baud_cnt[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFF000000000EEE0"
    )
        port map (
      I0 => \tx_baud_cnt[3]_i_2_n_0\,
      I1 => \tx_baud_cnt_reg_n_0_[4]\,
      I2 => \tx_state__0\(1),
      I3 => \tx_state__0\(0),
      I4 => \tx_baud_cnt_reg_n_0_[3]\,
      I5 => \tx_baud_cnt[3]_i_3_n_0\,
      O => tx_baud_cnt(3)
    );
\tx_baud_cnt[3]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \tx_baud_cnt_reg_n_0_[7]\,
      I1 => \tx_baud_cnt_reg_n_0_[8]\,
      I2 => \tx_baud_cnt_reg_n_0_[9]\,
      I3 => \tx_baud_cnt_reg_n_0_[6]\,
      I4 => \tx_baud_cnt_reg_n_0_[5]\,
      O => \tx_baud_cnt[3]_i_2_n_0\
    );
\tx_baud_cnt[3]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \tx_baud_cnt_reg_n_0_[1]\,
      I1 => \tx_baud_cnt_reg_n_0_[0]\,
      I2 => \tx_baud_cnt_reg_n_0_[2]\,
      O => \tx_baud_cnt[3]_i_3_n_0\
    );
\tx_baud_cnt[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9999999800000000"
    )
        port map (
      I0 => \tx_baud_cnt[4]_i_2_n_0\,
      I1 => \tx_baud_cnt_reg_n_0_[4]\,
      I2 => \tx_baud_cnt_reg_n_0_[5]\,
      I3 => \tx_baud_cnt_reg_n_0_[6]\,
      I4 => \tx_baud_cnt[6]_i_3_n_0\,
      I5 => \tx_baud_cnt[4]_i_3_n_0\,
      O => tx_baud_cnt(4)
    );
\tx_baud_cnt[4]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \tx_baud_cnt_reg_n_0_[2]\,
      I1 => \tx_baud_cnt_reg_n_0_[0]\,
      I2 => \tx_baud_cnt_reg_n_0_[1]\,
      I3 => \tx_baud_cnt_reg_n_0_[3]\,
      O => \tx_baud_cnt[4]_i_2_n_0\
    );
\tx_baud_cnt[4]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \tx_state__0\(0),
      I1 => \tx_state__0\(1),
      O => \tx_baud_cnt[4]_i_3_n_0\
    );
\tx_baud_cnt[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9998999899980000"
    )
        port map (
      I0 => \tx_baud_cnt[6]_i_2_n_0\,
      I1 => \tx_baud_cnt_reg_n_0_[5]\,
      I2 => \tx_baud_cnt_reg_n_0_[6]\,
      I3 => \tx_baud_cnt[6]_i_3_n_0\,
      I4 => \tx_state__0\(1),
      I5 => \tx_state__0\(0),
      O => tx_baud_cnt(5)
    );
\tx_baud_cnt[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A9A8A9A8A9A80000"
    )
        port map (
      I0 => \tx_baud_cnt_reg_n_0_[6]\,
      I1 => \tx_baud_cnt_reg_n_0_[5]\,
      I2 => \tx_baud_cnt[6]_i_2_n_0\,
      I3 => \tx_baud_cnt[6]_i_3_n_0\,
      I4 => \tx_state__0\(1),
      I5 => \tx_state__0\(0),
      O => tx_baud_cnt(6)
    );
\tx_baud_cnt[6]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \tx_baud_cnt_reg_n_0_[3]\,
      I1 => \tx_baud_cnt_reg_n_0_[1]\,
      I2 => \tx_baud_cnt_reg_n_0_[0]\,
      I3 => \tx_baud_cnt_reg_n_0_[2]\,
      I4 => \tx_baud_cnt_reg_n_0_[4]\,
      O => \tx_baud_cnt[6]_i_2_n_0\
    );
\tx_baud_cnt[6]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \tx_baud_cnt_reg_n_0_[9]\,
      I1 => \tx_baud_cnt_reg_n_0_[8]\,
      I2 => \tx_baud_cnt_reg_n_0_[7]\,
      O => \tx_baud_cnt[6]_i_3_n_0\
    );
\tx_baud_cnt[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9990999099908880"
    )
        port map (
      I0 => \tx_baud_cnt[9]_i_3_n_0\,
      I1 => \tx_baud_cnt_reg_n_0_[7]\,
      I2 => \tx_state__0\(1),
      I3 => \tx_state__0\(0),
      I4 => \tx_baud_cnt_reg_n_0_[9]\,
      I5 => \tx_baud_cnt_reg_n_0_[8]\,
      O => tx_baud_cnt(7)
    );
\tx_baud_cnt[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"E1E1E100E0E0E000"
    )
        port map (
      I0 => \tx_baud_cnt_reg_n_0_[7]\,
      I1 => \tx_baud_cnt[9]_i_3_n_0\,
      I2 => \tx_baud_cnt_reg_n_0_[8]\,
      I3 => \tx_state__0\(1),
      I4 => \tx_state__0\(0),
      I5 => \tx_baud_cnt_reg_n_0_[9]\,
      O => tx_baud_cnt(8)
    );
\tx_baud_cnt[9]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0E"
    )
        port map (
      I0 => \tx_state__0\(1),
      I1 => \tx_state__0\(0),
      I2 => rst,
      O => \tx_baud_cnt[9]_i_1_n_0\
    );
\tx_baud_cnt[9]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F1F1F1F1F1F1F11F"
    )
        port map (
      I0 => \tx_state__0\(0),
      I1 => \tx_state__0\(1),
      I2 => \tx_baud_cnt_reg_n_0_[9]\,
      I3 => \tx_baud_cnt_reg_n_0_[7]\,
      I4 => \tx_baud_cnt[9]_i_3_n_0\,
      I5 => \tx_baud_cnt_reg_n_0_[8]\,
      O => tx_baud_cnt(9)
    );
\tx_baud_cnt[9]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \tx_baud_cnt_reg_n_0_[6]\,
      I1 => \tx_baud_cnt_reg_n_0_[5]\,
      I2 => \tx_baud_cnt[6]_i_2_n_0\,
      O => \tx_baud_cnt[9]_i_3_n_0\
    );
\tx_baud_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \tx_baud_cnt[9]_i_1_n_0\,
      D => tx_baud_cnt(0),
      Q => \tx_baud_cnt_reg_n_0_[0]\,
      R => '0'
    );
\tx_baud_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \tx_baud_cnt[9]_i_1_n_0\,
      D => tx_baud_cnt(1),
      Q => \tx_baud_cnt_reg_n_0_[1]\,
      R => '0'
    );
\tx_baud_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \tx_baud_cnt[9]_i_1_n_0\,
      D => tx_baud_cnt(2),
      Q => \tx_baud_cnt_reg_n_0_[2]\,
      R => '0'
    );
\tx_baud_cnt_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \tx_baud_cnt[9]_i_1_n_0\,
      D => tx_baud_cnt(3),
      Q => \tx_baud_cnt_reg_n_0_[3]\,
      R => '0'
    );
\tx_baud_cnt_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \tx_baud_cnt[9]_i_1_n_0\,
      D => tx_baud_cnt(4),
      Q => \tx_baud_cnt_reg_n_0_[4]\,
      R => '0'
    );
\tx_baud_cnt_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \tx_baud_cnt[9]_i_1_n_0\,
      D => tx_baud_cnt(5),
      Q => \tx_baud_cnt_reg_n_0_[5]\,
      R => '0'
    );
\tx_baud_cnt_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \tx_baud_cnt[9]_i_1_n_0\,
      D => tx_baud_cnt(6),
      Q => \tx_baud_cnt_reg_n_0_[6]\,
      R => '0'
    );
\tx_baud_cnt_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \tx_baud_cnt[9]_i_1_n_0\,
      D => tx_baud_cnt(7),
      Q => \tx_baud_cnt_reg_n_0_[7]\,
      R => '0'
    );
\tx_baud_cnt_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \tx_baud_cnt[9]_i_1_n_0\,
      D => tx_baud_cnt(8),
      Q => \tx_baud_cnt_reg_n_0_[8]\,
      R => '0'
    );
\tx_baud_cnt_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \tx_baud_cnt[9]_i_1_n_0\,
      D => tx_baud_cnt(9),
      Q => \tx_baud_cnt_reg_n_0_[9]\,
      R => '0'
    );
\tx_bit_cnt[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFF7FF3F00080000"
    )
        port map (
      I0 => \FSM_sequential_tx_state[0]_i_2_n_0\,
      I1 => tx_reg_i_5_n_0,
      I2 => \tx_state__0\(0),
      I3 => rst,
      I4 => \tx_state__0\(1),
      I5 => \tx_bit_cnt_reg_n_0_[0]\,
      O => \tx_bit_cnt[0]_i_1_n_0\
    );
\tx_bit_cnt[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F80"
    )
        port map (
      I0 => \tx_bit_cnt_reg_n_0_[0]\,
      I1 => \tx_state__0\(1),
      I2 => \tx_bit_cnt[1]_i_2_n_0\,
      I3 => \tx_bit_cnt_reg_n_0_[1]\,
      O => \tx_bit_cnt[1]_i_1_n_0\
    );
\tx_bit_cnt[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0003000200020002"
    )
        port map (
      I0 => \tx_bit_cnt[1]_i_3_n_0\,
      I1 => \tx_baud_cnt[6]_i_3_n_0\,
      I2 => \tx_bit_cnt[1]_i_4_n_0\,
      I3 => \tx_baud_cnt[6]_i_2_n_0\,
      I4 => \tx_state__0\(0),
      I5 => \tx_bit_cnt[1]_i_5_n_0\,
      O => \tx_bit_cnt[1]_i_2_n_0\
    );
\tx_bit_cnt[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0004040404040404"
    )
        port map (
      I0 => rst,
      I1 => \tx_state__0\(1),
      I2 => \tx_state__0\(0),
      I3 => \tx_bit_cnt_reg_n_0_[2]\,
      I4 => \tx_bit_cnt_reg_n_0_[0]\,
      I5 => \tx_bit_cnt_reg_n_0_[1]\,
      O => \tx_bit_cnt[1]_i_3_n_0\
    );
\tx_bit_cnt[1]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \tx_baud_cnt_reg_n_0_[5]\,
      I1 => \tx_baud_cnt_reg_n_0_[6]\,
      O => \tx_bit_cnt[1]_i_4_n_0\
    );
\tx_bit_cnt[1]_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => rst,
      I1 => \tx_state__0\(1),
      O => \tx_bit_cnt[1]_i_5_n_0\
    );
\tx_bit_cnt[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAABAAAAA0AAA"
    )
        port map (
      I0 => \tx_bit_cnt_reg_n_0_[2]\,
      I1 => \tx_bit_cnt[2]_i_2_n_0\,
      I2 => tx_reg_i_5_n_0,
      I3 => \tx_state__0\(0),
      I4 => rst,
      I5 => \tx_state__0\(1),
      O => \tx_bit_cnt[2]_i_1_n_0\
    );
\tx_bit_cnt[2]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \tx_bit_cnt_reg_n_0_[0]\,
      I1 => \tx_bit_cnt_reg_n_0_[1]\,
      O => \tx_bit_cnt[2]_i_2_n_0\
    );
\tx_bit_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \tx_bit_cnt[0]_i_1_n_0\,
      Q => \tx_bit_cnt_reg_n_0_[0]\,
      R => '0'
    );
\tx_bit_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \tx_bit_cnt[1]_i_1_n_0\,
      Q => \tx_bit_cnt_reg_n_0_[1]\,
      R => '0'
    );
\tx_bit_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \tx_bit_cnt[2]_i_1_n_0\,
      Q => \tx_bit_cnt_reg_n_0_[2]\,
      R => '0'
    );
\tx_idx[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"46CCCCCC"
    )
        port map (
      I0 => \tx_state__0\(1),
      I1 => \tx_idx_reg_n_0_[0]\,
      I2 => \tx_idx_reg_n_0_[1]\,
      I3 => \tx_state__0\(0),
      I4 => tx_reg_i_5_n_0,
      O => \tx_idx[0]_i_1_n_0\
    );
\tx_idx[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"78F0F0F0"
    )
        port map (
      I0 => \tx_state__0\(1),
      I1 => \tx_idx_reg_n_0_[0]\,
      I2 => \tx_idx_reg_n_0_[1]\,
      I3 => \tx_state__0\(0),
      I4 => tx_reg_i_5_n_0,
      O => \tx_idx[1]_i_1_n_0\
    );
\tx_idx_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \tx_idx[0]_i_1_n_0\,
      Q => \tx_idx_reg_n_0_[0]\,
      R => rst
    );
\tx_idx_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \tx_idx[1]_i_1_n_0\,
      Q => \tx_idx_reg_n_0_[1]\,
      R => rst
    );
tx_reg_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FEFFFFFFFE000000"
    )
        port map (
      I0 => tx_reg_i_2_n_0,
      I1 => tx_reg_i_3_n_0,
      I2 => tx_reg_i_4_n_0,
      I3 => tx_reg_i_5_n_0,
      I4 => \tx_state__0\(1),
      I5 => \^tx\,
      O => tx_reg_i_1_n_0
    );
tx_reg_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0C00000088888888"
    )
        port map (
      I0 => tx_reg_i_6_n_0,
      I1 => tx_reg_i_7_n_0,
      I2 => \tx_bit_cnt_reg_n_0_[2]\,
      I3 => \tx_shift_reg_n_0_[3]\,
      I4 => \tx_bit_cnt_reg_n_0_[1]\,
      I5 => \tx_bit_cnt_reg_n_0_[0]\,
      O => tx_reg_i_2_n_0
    );
tx_reg_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF000080000000"
    )
        port map (
      I0 => \tx_bit_cnt_reg_n_0_[1]\,
      I1 => \tx_bit_cnt_reg_n_0_[0]\,
      I2 => \tx_bit_cnt_reg_n_0_[2]\,
      I3 => \tx_shift_reg_n_0_[7]\,
      I4 => tx_reg_i_7_n_0,
      I5 => tx_reg_i_8_n_0,
      O => tx_reg_i_3_n_0
    );
tx_reg_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0080"
    )
        port map (
      I0 => \tx_state__0\(1),
      I1 => \tx_state__0\(0),
      I2 => \tx_idx_reg_n_0_[1]\,
      I3 => \tx_idx_reg_n_0_[0]\,
      O => tx_reg_i_4_n_0
    );
tx_reg_i_5: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => \tx_baud_cnt[6]_i_2_n_0\,
      I1 => \tx_baud_cnt_reg_n_0_[5]\,
      I2 => \tx_baud_cnt_reg_n_0_[6]\,
      I3 => \tx_baud_cnt_reg_n_0_[7]\,
      I4 => \tx_baud_cnt_reg_n_0_[8]\,
      I5 => \tx_baud_cnt_reg_n_0_[9]\,
      O => tx_reg_i_5_n_0
    );
tx_reg_i_6: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \tx_shift_reg_n_0_[6]\,
      I1 => \tx_shift_reg_n_0_[2]\,
      I2 => \tx_bit_cnt_reg_n_0_[1]\,
      I3 => \tx_shift_reg_n_0_[4]\,
      I4 => \tx_bit_cnt_reg_n_0_[2]\,
      I5 => \tx_shift_reg_n_0_[0]\,
      O => tx_reg_i_6_n_0
    );
tx_reg_i_7: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \tx_state__0\(1),
      I1 => \tx_state__0\(0),
      O => tx_reg_i_7_n_0
    );
tx_reg_i_8: unisim.vcomponents.LUT5
    generic map(
      INIT => X"44400040"
    )
        port map (
      I0 => \tx_bit_cnt_reg_n_0_[1]\,
      I1 => \tx_bit_cnt_reg_n_0_[0]\,
      I2 => \tx_shift_reg_n_0_[1]\,
      I3 => \tx_bit_cnt_reg_n_0_[2]\,
      I4 => \tx_shift_reg_n_0_[5]\,
      O => tx_reg_i_8_n_0
    );
tx_reg_reg: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => clk,
      CE => '1',
      D => tx_reg_i_1_n_0,
      Q => \^tx\,
      S => rst
    );
\tx_shift[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0800080000000800"
    )
        port map (
      I0 => tx_reg_i_5_n_0,
      I1 => \tx_state__0\(0),
      I2 => rst,
      I3 => \tx_state__0\(1),
      I4 => \tx_idx_reg_n_0_[1]\,
      I5 => \tx_idx_reg_n_0_[0]\,
      O => \tx_shift[7]_i_1_n_0\
    );
\tx_shift[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00B0000000000000"
    )
        port map (
      I0 => \tx_idx_reg_n_0_[0]\,
      I1 => \tx_idx_reg_n_0_[1]\,
      I2 => \tx_state__0\(1),
      I3 => rst,
      I4 => \tx_state__0\(0),
      I5 => tx_reg_i_5_n_0,
      O => \tx_shift[7]_i_2_n_0\
    );
\tx_shift_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \tx_shift[7]_i_2_n_0\,
      D => \^reg8_out\(0),
      Q => \tx_shift_reg_n_0_[0]\,
      R => \tx_shift[7]_i_1_n_0\
    );
\tx_shift_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \tx_shift[7]_i_2_n_0\,
      D => \^reg8_out\(1),
      Q => \tx_shift_reg_n_0_[1]\,
      R => \tx_shift[7]_i_1_n_0\
    );
\tx_shift_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \tx_shift[7]_i_2_n_0\,
      D => \^reg8_out\(2),
      Q => \tx_shift_reg_n_0_[2]\,
      R => \tx_shift[7]_i_1_n_0\
    );
\tx_shift_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \tx_shift[7]_i_2_n_0\,
      D => \^reg8_out\(3),
      Q => \tx_shift_reg_n_0_[3]\,
      R => \tx_shift[7]_i_1_n_0\
    );
\tx_shift_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \tx_shift[7]_i_2_n_0\,
      D => \^reg8_out\(4),
      Q => \tx_shift_reg_n_0_[4]\,
      R => \tx_shift[7]_i_1_n_0\
    );
\tx_shift_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \tx_shift[7]_i_2_n_0\,
      D => \^reg8_out\(5),
      Q => \tx_shift_reg_n_0_[5]\,
      R => \tx_shift[7]_i_1_n_0\
    );
\tx_shift_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \tx_shift[7]_i_2_n_0\,
      D => \^reg8_out\(6),
      Q => \tx_shift_reg_n_0_[6]\,
      R => \tx_shift[7]_i_1_n_0\
    );
\tx_shift_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \tx_shift[7]_i_2_n_0\,
      D => \^reg8_out\(7),
      Q => \tx_shift_reg_n_0_[7]\,
      R => \tx_shift[7]_i_1_n_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity FNPLL_uart_rx_tx_regs_0_0 is
  port (
    clk : in STD_LOGIC;
    rst : in STD_LOGIC;
    rx : in STD_LOGIC;
    tx : out STD_LOGIC;
    reg8_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
    reg16_out : out STD_LOGIC_VECTOR ( 15 downto 0 );
    new_data : out STD_LOGIC
  );
  attribute NotValidForBitStream : boolean;
  attribute NotValidForBitStream of FNPLL_uart_rx_tx_regs_0_0 : entity is true;
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of FNPLL_uart_rx_tx_regs_0_0 : entity is "FNPLL_uart_rx_tx_regs_0_0,uart_rx_tx_regs,{}";
  attribute downgradeipidentifiedwarnings : string;
  attribute downgradeipidentifiedwarnings of FNPLL_uart_rx_tx_regs_0_0 : entity is "yes";
  attribute ip_definition_source : string;
  attribute ip_definition_source of FNPLL_uart_rx_tx_regs_0_0 : entity is "module_ref";
  attribute x_core_info : string;
  attribute x_core_info of FNPLL_uart_rx_tx_regs_0_0 : entity is "uart_rx_tx_regs,Vivado 2025.1";
end FNPLL_uart_rx_tx_regs_0_0;

architecture STRUCTURE of FNPLL_uart_rx_tx_regs_0_0 is
  attribute x_interface_info : string;
  attribute x_interface_info of clk : signal is "xilinx.com:signal:clock:1.0 clk CLK";
  attribute x_interface_mode : string;
  attribute x_interface_mode of clk : signal is "slave clk";
  attribute x_interface_parameter : string;
  attribute x_interface_parameter of clk : signal is "XIL_INTERFACENAME clk, ASSOCIATED_RESET rst, FREQ_HZ 5000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, INSERT_VIP 0";
  attribute x_interface_info of rst : signal is "xilinx.com:signal:reset:1.0 rst RST";
  attribute x_interface_mode of rst : signal is "slave rst";
  attribute x_interface_parameter of rst : signal is "XIL_INTERFACENAME rst, POLARITY ACTIVE_LOW, INSERT_VIP 0";
begin
U0: entity work.FNPLL_uart_rx_tx_regs_0_0_uart_rx_tx_regs
     port map (
      clk => clk,
      new_data => new_data,
      reg16_out(15 downto 0) => reg16_out(15 downto 0),
      reg8_out(7 downto 0) => reg8_out(7 downto 0),
      rst => rst,
      rx => rx,
      tx => tx
    );
end STRUCTURE;
