library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity display_3bit_7seg_digit is
    port(
        number : in  unsigned(2 downto 0);  -- 3-bit number 0..7
        seg    : out std_logic_vector(6 downto 0); -- segments a-g
        dp     : out std_logic;                     -- decimal point
        an     : out std_logic_vector(3 downto 0)  -- digit enables
    );
end entity;

architecture rtl of display_3bit_7seg_digit is
begin
    -- Always enable only digit 0
    an <= "1110";  -- active low: an[0]=0, others=1

    -- Decimal point off
    dp <= '1';  -- active low on Basys 3, so '1' = off

    -- 7-segment decoder for numbers 0..7
    process(number)
    begin
        case number is
            when "000" => seg <= "1000000"; -- 0
            when "001" => seg <= "1111001"; -- 1
            when "010" => seg <= "0100100"; -- 2
            when "011" => seg <= "0110000"; -- 3
            when "100" => seg <= "0011001"; -- 4
            when "101" => seg <= "0010010"; -- 5
            when "110" => seg <= "0000010"; -- 6
            when "111" => seg <= "1111000"; -- 7
            when others => seg <= "1111111"; -- blank
        end case;
    end process;
end architecture;
