--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
--Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2025.1 (win64) Build 6140274 Thu May 22 00:12:29 MDT 2025
--Date        : Sun Jan  4 13:06:08 2026
--Host        : LAPTOP-L3CRKKNJ running 64-bit major release  (build 9200)
--Command     : generate_target FNPLL_wrapper.bd
--Design      : FNPLL_wrapper
--Purpose     : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity FNPLL_wrapper is
  port (
    DS_OUT : out STD_LOGIC_VECTOR ( 0 to 0 );
    D_BG : out STD_LOGIC_VECTOR ( 0 to 0 );
    UART_IN : in STD_LOGIC;
    UART_OUT : out STD_LOGIC;
    VCO_INN : in STD_LOGIC;
    an : out STD_LOGIC_VECTOR ( 3 downto 0 );
    c_out : out STD_LOGIC;
    dp : out STD_LOGIC;
    led : out STD_LOGIC;
    seg : out STD_LOGIC_VECTOR ( 6 downto 0 );
    sys_clock : in STD_LOGIC
  );
end FNPLL_wrapper;

architecture STRUCTURE of FNPLL_wrapper is
  component FNPLL is
  port (
    DS_OUT : out STD_LOGIC_VECTOR ( 0 to 0 );
    UART_IN : in STD_LOGIC;
    seg : out STD_LOGIC_VECTOR ( 6 downto 0 );
    an : out STD_LOGIC_VECTOR ( 3 downto 0 );
    dp : out STD_LOGIC;
    UART_OUT : out STD_LOGIC;
    sys_clock : in STD_LOGIC;
    D_BG : out STD_LOGIC_VECTOR ( 0 to 0 );
    c_out : out STD_LOGIC;
    led : out STD_LOGIC;
    VCO_INN : in STD_LOGIC
  );
  end component FNPLL;
begin
FNPLL_i: component FNPLL
     port map (
      DS_OUT(0) => DS_OUT(0),
      D_BG(0) => D_BG(0),
      UART_IN => UART_IN,
      UART_OUT => UART_OUT,
      VCO_INN => VCO_INN,
      an(3 downto 0) => an(3 downto 0),
      c_out => c_out,
      dp => dp,
      led => led,
      seg(6 downto 0) => seg(6 downto 0),
      sys_clock => sys_clock
    );
end STRUCTURE;
