library ieee;
use ieee.std_logic_1164.all;

entity pass_through is
    port (
        clk   : in  std_logic;  -- clock input
        din   : in  std_logic;  -- data input
        dout  : out std_logic   -- output = input when clk high
    );
end entity pass_through;

architecture rtl of pass_through is
begin
    process(clk)
    begin
        if rising_edge(clk) then
            dout <= din;  -- latch input to output on clock rising edge
        end if;
    end process;
end architecture rtl;