-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2025.1 (win64) Build 6140274 Thu May 22 00:12:29 MDT 2025
-- Date        : Sun Jan  4 04:34:43 2026
-- Host        : LAPTOP-L3CRKKNJ running 64-bit major release  (build 9200)
-- Command     : write_vhdl -force -mode funcsim
--               c:/Vivado_Debug/PLLXplore_FNPLL/FNPLL2.gen/sources_1/bd/FNPLL/ip/FNPLL_nn2_div_0_0/FNPLL_nn2_div_0_0_sim_netlist.vhdl
-- Design      : FNPLL_nn2_div_0_0
-- Purpose     : This VHDL netlist is a functional simulation representation of the design and should not be modified or
--               synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device      : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity FNPLL_nn2_div_0_0_nn2_div is
  port (
    out_pulse : out STD_LOGIC;
    count_val : in STD_LOGIC_VECTOR ( 7 downto 0 );
    vcoin : in STD_LOGIC;
    select_bit : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of FNPLL_nn2_div_0_0_nn2_div : entity is "nn2_div";
end FNPLL_nn2_div_0_0_nn2_div;

architecture STRUCTURE of FNPLL_nn2_div_0_0_nn2_div is
  signal \counter[1]_i_1_n_0\ : STD_LOGIC;
  signal \counter[2]_i_1_n_0\ : STD_LOGIC;
  signal \counter[3]_i_1_n_0\ : STD_LOGIC;
  signal \counter[4]_i_1_n_0\ : STD_LOGIC;
  signal \counter[5]_i_1_n_0\ : STD_LOGIC;
  signal \counter[6]_i_1_n_0\ : STD_LOGIC;
  signal \counter[7]_i_1_n_0\ : STD_LOGIC;
  signal \counter[8]_i_1_n_0\ : STD_LOGIC;
  signal \counter[9]_i_2_n_0\ : STD_LOGIC;
  signal counter_reg : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal current_base_n : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal \current_base_n[1]_i_1_n_0\ : STD_LOGIC;
  signal \current_base_n[2]_i_1_n_0\ : STD_LOGIC;
  signal \current_base_n[3]_i_1_n_0\ : STD_LOGIC;
  signal \current_base_n[4]_i_1_n_0\ : STD_LOGIC;
  signal \current_base_n[5]_i_1_n_0\ : STD_LOGIC;
  signal \current_base_n[6]_i_1_n_0\ : STD_LOGIC;
  signal \current_base_n[7]_i_1_n_0\ : STD_LOGIC;
  signal \current_base_n[8]_i_1_n_0\ : STD_LOGIC;
  signal \current_base_n[8]_i_2_n_0\ : STD_LOGIC;
  signal current_limit : STD_LOGIC_VECTOR ( 9 downto 2 );
  signal \current_limit[9]_i_2_n_0\ : STD_LOGIC;
  signal \current_limit_reg_n_0_[0]\ : STD_LOGIC;
  signal \current_limit_reg_n_0_[1]\ : STD_LOGIC;
  signal \current_limit_reg_n_0_[2]\ : STD_LOGIC;
  signal \current_limit_reg_n_0_[3]\ : STD_LOGIC;
  signal \current_limit_reg_n_0_[4]\ : STD_LOGIC;
  signal \current_limit_reg_n_0_[5]\ : STD_LOGIC;
  signal \current_limit_reg_n_0_[6]\ : STD_LOGIC;
  signal \current_limit_reg_n_0_[7]\ : STD_LOGIC;
  signal \current_limit_reg_n_0_[8]\ : STD_LOGIC;
  signal \current_limit_reg_n_0_[9]\ : STD_LOGIC;
  signal current_mode : STD_LOGIC;
  signal minusOp : STD_LOGIC_VECTOR ( 0 to 0 );
  signal out_pulse0_carry_i_1_n_0 : STD_LOGIC;
  signal out_pulse0_carry_i_2_n_0 : STD_LOGIC;
  signal out_pulse0_carry_i_3_n_0 : STD_LOGIC;
  signal out_pulse0_carry_i_4_n_0 : STD_LOGIC;
  signal out_pulse0_carry_i_5_n_0 : STD_LOGIC;
  signal out_pulse0_carry_i_6_n_0 : STD_LOGIC;
  signal out_pulse0_carry_i_7_n_0 : STD_LOGIC;
  signal out_pulse0_carry_i_8_n_0 : STD_LOGIC;
  signal out_pulse0_carry_i_9_n_0 : STD_LOGIC;
  signal out_pulse0_carry_n_0 : STD_LOGIC;
  signal out_pulse0_carry_n_1 : STD_LOGIC;
  signal out_pulse0_carry_n_2 : STD_LOGIC;
  signal out_pulse0_carry_n_3 : STD_LOGIC;
  signal plusOp : STD_LOGIC_VECTOR ( 9 to 9 );
  signal \plusOp__0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal toggle : STD_LOGIC;
  signal toggle_i_1_n_0 : STD_LOGIC;
  signal NLW_out_pulse0_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \counter[1]_i_1\ : label is "soft_lutpair9";
  attribute SOFT_HLUTNM of \counter[2]_i_1\ : label is "soft_lutpair4";
  attribute SOFT_HLUTNM of \counter[3]_i_1\ : label is "soft_lutpair2";
  attribute SOFT_HLUTNM of \counter[5]_i_1\ : label is "soft_lutpair8";
  attribute SOFT_HLUTNM of \counter[7]_i_1\ : label is "soft_lutpair1";
  attribute SOFT_HLUTNM of \counter[9]_i_2\ : label is "soft_lutpair2";
  attribute SOFT_HLUTNM of \current_base_n[1]_i_1\ : label is "soft_lutpair6";
  attribute SOFT_HLUTNM of \current_base_n[2]_i_1\ : label is "soft_lutpair6";
  attribute SOFT_HLUTNM of \current_base_n[3]_i_1\ : label is "soft_lutpair0";
  attribute SOFT_HLUTNM of \current_base_n[4]_i_1\ : label is "soft_lutpair0";
  attribute SOFT_HLUTNM of \current_base_n[7]_i_1\ : label is "soft_lutpair7";
  attribute SOFT_HLUTNM of \current_base_n[8]_i_1\ : label is "soft_lutpair7";
  attribute SOFT_HLUTNM of \current_limit[3]_i_1\ : label is "soft_lutpair3";
  attribute SOFT_HLUTNM of \current_limit[4]_i_1\ : label is "soft_lutpair3";
  attribute SOFT_HLUTNM of \current_limit[6]_i_1\ : label is "soft_lutpair10";
  attribute SOFT_HLUTNM of \current_limit[7]_i_1\ : label is "soft_lutpair10";
  attribute SOFT_HLUTNM of \current_limit[8]_i_1\ : label is "soft_lutpair5";
  attribute SOFT_HLUTNM of \current_limit[9]_i_1\ : label is "soft_lutpair5";
  attribute SOFT_HLUTNM of out_pulse0_carry_i_5 : label is "soft_lutpair1";
  attribute SOFT_HLUTNM of out_pulse0_carry_i_8 : label is "soft_lutpair8";
  attribute SOFT_HLUTNM of out_pulse0_carry_i_9 : label is "soft_lutpair4";
  attribute SOFT_HLUTNM of toggle_i_1 : label is "soft_lutpair9";
begin
\counter[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => counter_reg(0),
      O => \plusOp__0\(0)
    );
\counter[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"06"
    )
        port map (
      I0 => counter_reg(0),
      I1 => counter_reg(1),
      I2 => out_pulse0_carry_n_0,
      O => \counter[1]_i_1_n_0\
    );
\counter[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0078"
    )
        port map (
      I0 => counter_reg(0),
      I1 => counter_reg(1),
      I2 => counter_reg(2),
      I3 => out_pulse0_carry_n_0,
      O => \counter[2]_i_1_n_0\
    );
\counter[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => counter_reg(2),
      I1 => counter_reg(0),
      I2 => counter_reg(1),
      I3 => counter_reg(3),
      O => \counter[3]_i_1_n_0\
    );
\counter[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000007FFF8000"
    )
        port map (
      I0 => counter_reg(2),
      I1 => counter_reg(0),
      I2 => counter_reg(1),
      I3 => counter_reg(3),
      I4 => counter_reg(4),
      I5 => out_pulse0_carry_n_0,
      O => \counter[4]_i_1_n_0\
    );
\counter[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"09"
    )
        port map (
      I0 => \counter[9]_i_2_n_0\,
      I1 => counter_reg(5),
      I2 => out_pulse0_carry_n_0,
      O => \counter[5]_i_1_n_0\
    );
\counter[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D2"
    )
        port map (
      I0 => counter_reg(5),
      I1 => \counter[9]_i_2_n_0\,
      I2 => counter_reg(6),
      O => \counter[6]_i_1_n_0\
    );
\counter[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000DF20"
    )
        port map (
      I0 => counter_reg(5),
      I1 => \counter[9]_i_2_n_0\,
      I2 => counter_reg(6),
      I3 => counter_reg(7),
      I4 => out_pulse0_carry_n_0,
      O => \counter[7]_i_1_n_0\
    );
\counter[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000DFFF2000"
    )
        port map (
      I0 => counter_reg(6),
      I1 => \counter[9]_i_2_n_0\,
      I2 => counter_reg(5),
      I3 => counter_reg(7),
      I4 => counter_reg(8),
      I5 => out_pulse0_carry_n_0,
      O => \counter[8]_i_1_n_0\
    );
\counter[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F7FFFFFF08000000"
    )
        port map (
      I0 => counter_reg(8),
      I1 => counter_reg(6),
      I2 => \counter[9]_i_2_n_0\,
      I3 => counter_reg(5),
      I4 => counter_reg(7),
      I5 => counter_reg(9),
      O => plusOp(9)
    );
\counter[9]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFFFFFF"
    )
        port map (
      I0 => counter_reg(3),
      I1 => counter_reg(1),
      I2 => counter_reg(0),
      I3 => counter_reg(2),
      I4 => counter_reg(4),
      O => \counter[9]_i_2_n_0\
    );
\counter_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => vcoin,
      CE => '1',
      D => \plusOp__0\(0),
      Q => counter_reg(0),
      R => out_pulse0_carry_n_0
    );
\counter_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => vcoin,
      CE => '1',
      D => \counter[1]_i_1_n_0\,
      Q => counter_reg(1),
      R => '0'
    );
\counter_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => vcoin,
      CE => '1',
      D => \counter[2]_i_1_n_0\,
      Q => counter_reg(2),
      R => '0'
    );
\counter_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => vcoin,
      CE => '1',
      D => \counter[3]_i_1_n_0\,
      Q => counter_reg(3),
      R => out_pulse0_carry_n_0
    );
\counter_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => vcoin,
      CE => '1',
      D => \counter[4]_i_1_n_0\,
      Q => counter_reg(4),
      R => '0'
    );
\counter_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => vcoin,
      CE => '1',
      D => \counter[5]_i_1_n_0\,
      Q => counter_reg(5),
      R => '0'
    );
\counter_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => vcoin,
      CE => '1',
      D => \counter[6]_i_1_n_0\,
      Q => counter_reg(6),
      R => out_pulse0_carry_n_0
    );
\counter_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => vcoin,
      CE => '1',
      D => \counter[7]_i_1_n_0\,
      Q => counter_reg(7),
      R => '0'
    );
\counter_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => vcoin,
      CE => '1',
      D => \counter[8]_i_1_n_0\,
      Q => counter_reg(8),
      R => '0'
    );
\counter_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => vcoin,
      CE => '1',
      D => plusOp(9),
      Q => counter_reg(9),
      R => out_pulse0_carry_n_0
    );
\current_base_n[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => count_val(0),
      O => minusOp(0)
    );
\current_base_n[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => count_val(0),
      I1 => count_val(1),
      O => \current_base_n[1]_i_1_n_0\
    );
\current_base_n[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E1"
    )
        port map (
      I0 => count_val(1),
      I1 => count_val(0),
      I2 => count_val(2),
      O => \current_base_n[2]_i_1_n_0\
    );
\current_base_n[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FE01"
    )
        port map (
      I0 => count_val(2),
      I1 => count_val(0),
      I2 => count_val(1),
      I3 => count_val(3),
      O => \current_base_n[3]_i_1_n_0\
    );
\current_base_n[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0001"
    )
        port map (
      I0 => count_val(3),
      I1 => count_val(1),
      I2 => count_val(0),
      I3 => count_val(2),
      I4 => count_val(4),
      O => \current_base_n[4]_i_1_n_0\
    );
\current_base_n[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFE00000001"
    )
        port map (
      I0 => count_val(4),
      I1 => count_val(2),
      I2 => count_val(0),
      I3 => count_val(1),
      I4 => count_val(3),
      I5 => count_val(5),
      O => \current_base_n[5]_i_1_n_0\
    );
\current_base_n[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \current_base_n[8]_i_2_n_0\,
      I1 => count_val(6),
      O => \current_base_n[6]_i_1_n_0\
    );
\current_base_n[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E1"
    )
        port map (
      I0 => count_val(6),
      I1 => \current_base_n[8]_i_2_n_0\,
      I2 => count_val(7),
      O => \current_base_n[7]_i_1_n_0\
    );
\current_base_n[8]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => count_val(6),
      I1 => \current_base_n[8]_i_2_n_0\,
      I2 => count_val(7),
      O => \current_base_n[8]_i_1_n_0\
    );
\current_base_n[8]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => count_val(4),
      I1 => count_val(2),
      I2 => count_val(0),
      I3 => count_val(1),
      I4 => count_val(3),
      I5 => count_val(5),
      O => \current_base_n[8]_i_2_n_0\
    );
\current_base_n_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => vcoin,
      CE => out_pulse0_carry_n_0,
      D => minusOp(0),
      Q => current_base_n(0),
      R => '0'
    );
\current_base_n_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => vcoin,
      CE => out_pulse0_carry_n_0,
      D => \current_base_n[1]_i_1_n_0\,
      Q => current_base_n(1),
      R => '0'
    );
\current_base_n_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => vcoin,
      CE => out_pulse0_carry_n_0,
      D => \current_base_n[2]_i_1_n_0\,
      Q => current_base_n(2),
      R => '0'
    );
\current_base_n_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => vcoin,
      CE => out_pulse0_carry_n_0,
      D => \current_base_n[3]_i_1_n_0\,
      Q => current_base_n(3),
      R => '0'
    );
\current_base_n_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => vcoin,
      CE => out_pulse0_carry_n_0,
      D => \current_base_n[4]_i_1_n_0\,
      Q => current_base_n(4),
      R => '0'
    );
\current_base_n_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => vcoin,
      CE => out_pulse0_carry_n_0,
      D => \current_base_n[5]_i_1_n_0\,
      Q => current_base_n(5),
      R => '0'
    );
\current_base_n_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => vcoin,
      CE => out_pulse0_carry_n_0,
      D => \current_base_n[6]_i_1_n_0\,
      Q => current_base_n(6),
      R => '0'
    );
\current_base_n_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => vcoin,
      CE => out_pulse0_carry_n_0,
      D => \current_base_n[7]_i_1_n_0\,
      Q => current_base_n(7),
      R => '0'
    );
\current_base_n_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => vcoin,
      CE => out_pulse0_carry_n_0,
      D => \current_base_n[8]_i_1_n_0\,
      Q => current_base_n(8),
      R => '0'
    );
\current_limit[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => current_mode,
      I1 => toggle,
      I2 => current_base_n(2),
      O => current_limit(2)
    );
\current_limit[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => current_base_n(2),
      I1 => toggle,
      I2 => current_mode,
      I3 => current_base_n(3),
      O => current_limit(3)
    );
\current_limit[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => current_base_n(3),
      I1 => current_mode,
      I2 => toggle,
      I3 => current_base_n(2),
      I4 => current_base_n(4),
      O => current_limit(4)
    );
\current_limit[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFF80000000"
    )
        port map (
      I0 => current_base_n(4),
      I1 => current_base_n(2),
      I2 => toggle,
      I3 => current_mode,
      I4 => current_base_n(3),
      I5 => current_base_n(5),
      O => current_limit(5)
    );
\current_limit[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \current_limit[9]_i_2_n_0\,
      I1 => current_base_n(6),
      O => current_limit(6)
    );
\current_limit[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D2"
    )
        port map (
      I0 => current_base_n(6),
      I1 => \current_limit[9]_i_2_n_0\,
      I2 => current_base_n(7),
      O => current_limit(7)
    );
\current_limit[8]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"DF20"
    )
        port map (
      I0 => current_base_n(7),
      I1 => \current_limit[9]_i_2_n_0\,
      I2 => current_base_n(6),
      I3 => current_base_n(8),
      O => current_limit(8)
    );
\current_limit[9]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"DF00"
    )
        port map (
      I0 => current_base_n(7),
      I1 => \current_limit[9]_i_2_n_0\,
      I2 => current_base_n(6),
      I3 => current_base_n(8),
      O => current_limit(9)
    );
\current_limit[9]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFFFFFFFFFF"
    )
        port map (
      I0 => current_base_n(4),
      I1 => current_base_n(2),
      I2 => toggle,
      I3 => current_mode,
      I4 => current_base_n(3),
      I5 => current_base_n(5),
      O => \current_limit[9]_i_2_n_0\
    );
\current_limit_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => vcoin,
      CE => '1',
      D => current_base_n(0),
      Q => \current_limit_reg_n_0_[0]\,
      R => '0'
    );
\current_limit_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => vcoin,
      CE => '1',
      D => current_base_n(1),
      Q => \current_limit_reg_n_0_[1]\,
      R => '0'
    );
\current_limit_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => vcoin,
      CE => '1',
      D => current_limit(2),
      Q => \current_limit_reg_n_0_[2]\,
      R => '0'
    );
\current_limit_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => vcoin,
      CE => '1',
      D => current_limit(3),
      Q => \current_limit_reg_n_0_[3]\,
      R => '0'
    );
\current_limit_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => vcoin,
      CE => '1',
      D => current_limit(4),
      Q => \current_limit_reg_n_0_[4]\,
      R => '0'
    );
\current_limit_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => vcoin,
      CE => '1',
      D => current_limit(5),
      Q => \current_limit_reg_n_0_[5]\,
      R => '0'
    );
\current_limit_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => vcoin,
      CE => '1',
      D => current_limit(6),
      Q => \current_limit_reg_n_0_[6]\,
      R => '0'
    );
\current_limit_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => vcoin,
      CE => '1',
      D => current_limit(7),
      Q => \current_limit_reg_n_0_[7]\,
      R => '0'
    );
\current_limit_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => vcoin,
      CE => '1',
      D => current_limit(8),
      Q => \current_limit_reg_n_0_[8]\,
      R => '0'
    );
\current_limit_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => vcoin,
      CE => '1',
      D => current_limit(9),
      Q => \current_limit_reg_n_0_[9]\,
      R => '0'
    );
current_mode_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => vcoin,
      CE => out_pulse0_carry_n_0,
      D => select_bit,
      Q => current_mode,
      R => '0'
    );
out_pulse0_carry: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => out_pulse0_carry_n_0,
      CO(2) => out_pulse0_carry_n_1,
      CO(1) => out_pulse0_carry_n_2,
      CO(0) => out_pulse0_carry_n_3,
      CYINIT => '1',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => NLW_out_pulse0_carry_O_UNCONNECTED(3 downto 0),
      S(3) => out_pulse0_carry_i_1_n_0,
      S(2) => out_pulse0_carry_i_2_n_0,
      S(1) => out_pulse0_carry_i_3_n_0,
      S(0) => out_pulse0_carry_i_4_n_0
    );
out_pulse0_carry_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9699"
    )
        port map (
      I0 => \current_limit_reg_n_0_[9]\,
      I1 => counter_reg(9),
      I2 => out_pulse0_carry_i_5_n_0,
      I3 => counter_reg(8),
      O => out_pulse0_carry_i_1_n_0
    );
out_pulse0_carry_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8200008200248200"
    )
        port map (
      I0 => out_pulse0_carry_i_6_n_0,
      I1 => counter_reg(7),
      I2 => \current_limit_reg_n_0_[7]\,
      I3 => \current_limit_reg_n_0_[6]\,
      I4 => counter_reg(6),
      I5 => out_pulse0_carry_i_7_n_0,
      O => out_pulse0_carry_i_2_n_0
    );
out_pulse0_carry_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8200008200248200"
    )
        port map (
      I0 => out_pulse0_carry_i_8_n_0,
      I1 => counter_reg(4),
      I2 => \current_limit_reg_n_0_[4]\,
      I3 => \current_limit_reg_n_0_[3]\,
      I4 => counter_reg(3),
      I5 => out_pulse0_carry_i_9_n_0,
      O => out_pulse0_carry_i_3_n_0
    );
out_pulse0_carry_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0920004000400920"
    )
        port map (
      I0 => \current_limit_reg_n_0_[1]\,
      I1 => counter_reg(1),
      I2 => counter_reg(0),
      I3 => \current_limit_reg_n_0_[0]\,
      I4 => \current_limit_reg_n_0_[2]\,
      I5 => counter_reg(2),
      O => out_pulse0_carry_i_4_n_0
    );
out_pulse0_carry_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"DFFF"
    )
        port map (
      I0 => counter_reg(6),
      I1 => \counter[9]_i_2_n_0\,
      I2 => counter_reg(5),
      I3 => counter_reg(7),
      O => out_pulse0_carry_i_5_n_0
    );
out_pulse0_carry_i_6: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => counter_reg(8),
      I1 => \current_limit_reg_n_0_[8]\,
      O => out_pulse0_carry_i_6_n_0
    );
out_pulse0_carry_i_7: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFFFFFFFFFF"
    )
        port map (
      I0 => counter_reg(4),
      I1 => counter_reg(2),
      I2 => counter_reg(0),
      I3 => counter_reg(1),
      I4 => counter_reg(3),
      I5 => counter_reg(5),
      O => out_pulse0_carry_i_7_n_0
    );
out_pulse0_carry_i_8: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => counter_reg(5),
      I1 => \current_limit_reg_n_0_[5]\,
      O => out_pulse0_carry_i_8_n_0
    );
out_pulse0_carry_i_9: unisim.vcomponents.LUT3
    generic map(
      INIT => X"7F"
    )
        port map (
      I0 => counter_reg(1),
      I1 => counter_reg(0),
      I2 => counter_reg(2),
      O => out_pulse0_carry_i_9_n_0
    );
out_pulse_reg: unisim.vcomponents.FDRE
     port map (
      C => vcoin,
      CE => '1',
      D => out_pulse0_carry_n_0,
      Q => out_pulse,
      R => '0'
    );
toggle_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => current_mode,
      I1 => out_pulse0_carry_n_0,
      I2 => toggle,
      O => toggle_i_1_n_0
    );
toggle_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => vcoin,
      CE => '1',
      D => toggle_i_1_n_0,
      Q => toggle,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity FNPLL_nn2_div_0_0 is
  port (
    vcoin : in STD_LOGIC;
    select_bit : in STD_LOGIC;
    count_val : in STD_LOGIC_VECTOR ( 7 downto 0 );
    out_pulse : out STD_LOGIC
  );
  attribute NotValidForBitStream : boolean;
  attribute NotValidForBitStream of FNPLL_nn2_div_0_0 : entity is true;
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of FNPLL_nn2_div_0_0 : entity is "FNPLL_nn2_div_0_0,nn2_div,{}";
  attribute downgradeipidentifiedwarnings : string;
  attribute downgradeipidentifiedwarnings of FNPLL_nn2_div_0_0 : entity is "yes";
  attribute ip_definition_source : string;
  attribute ip_definition_source of FNPLL_nn2_div_0_0 : entity is "module_ref";
  attribute x_core_info : string;
  attribute x_core_info of FNPLL_nn2_div_0_0 : entity is "nn2_div,Vivado 2025.1";
end FNPLL_nn2_div_0_0;

architecture STRUCTURE of FNPLL_nn2_div_0_0 is
begin
U0: entity work.FNPLL_nn2_div_0_0_nn2_div
     port map (
      count_val(7 downto 0) => count_val(7 downto 0),
      out_pulse => out_pulse,
      select_bit => select_bit,
      vcoin => vcoin
    );
end STRUCTURE;
