-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2025.1 (win64) Build 6140274 Thu May 22 00:12:29 MDT 2025
-- Date        : Sat Dec 20 19:37:03 2025
-- Host        : LAPTOP-L3CRKKNJ running 64-bit major release  (build 9200)
-- Command     : write_vhdl -force -mode funcsim
--               c:/Vivado_Debug/FNPLL8/FNPLL2.gen/sources_1/bd/FNPLL/ip/FNPLL_nn2_div_0_0/FNPLL_nn2_div_0_0_sim_netlist.vhdl
-- Design      : FNPLL_nn2_div_0_0
-- Purpose     : This VHDL netlist is a functional simulation representation of the design and should not be modified or
--               synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device      : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity FNPLL_nn2_div_0_0_nn2_div is
  port (
    out_pulse : out STD_LOGIC;
    select_bit : in STD_LOGIC;
    clk : in STD_LOGIC;
    count_val : in STD_LOGIC_VECTOR ( 7 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of FNPLL_nn2_div_0_0_nn2_div : entity is "nn2_div";
end FNPLL_nn2_div_0_0_nn2_div;

architecture STRUCTURE of FNPLL_nn2_div_0_0_nn2_div is
  signal base_n : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \counter[9]_i_2_n_0\ : STD_LOGIC;
  signal counter_reg : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal current_limit : STD_LOGIC_VECTOR ( 8 downto 1 );
  signal \current_limit[8]_i_2_n_0\ : STD_LOGIC;
  signal \current_limit_reg_n_0_[0]\ : STD_LOGIC;
  signal \current_limit_reg_n_0_[1]\ : STD_LOGIC;
  signal \current_limit_reg_n_0_[2]\ : STD_LOGIC;
  signal \current_limit_reg_n_0_[3]\ : STD_LOGIC;
  signal \current_limit_reg_n_0_[4]\ : STD_LOGIC;
  signal \current_limit_reg_n_0_[5]\ : STD_LOGIC;
  signal \current_limit_reg_n_0_[6]\ : STD_LOGIC;
  signal \current_limit_reg_n_0_[7]\ : STD_LOGIC;
  signal \current_limit_reg_n_0_[8]\ : STD_LOGIC;
  signal current_mode : STD_LOGIC;
  signal current_mode0 : STD_LOGIC;
  signal current_mode0_carry_i_1_n_0 : STD_LOGIC;
  signal current_mode0_carry_i_2_n_0 : STD_LOGIC;
  signal current_mode0_carry_i_3_n_0 : STD_LOGIC;
  signal current_mode0_carry_i_4_n_0 : STD_LOGIC;
  signal current_mode0_carry_n_1 : STD_LOGIC;
  signal current_mode0_carry_n_2 : STD_LOGIC;
  signal current_mode0_carry_n_3 : STD_LOGIC;
  signal current_mode_i_1_n_0 : STD_LOGIC;
  signal next_mode : STD_LOGIC;
  signal out_pulse0 : STD_LOGIC;
  signal out_pulse0_carry_i_10_n_0 : STD_LOGIC;
  signal out_pulse0_carry_i_1_n_0 : STD_LOGIC;
  signal out_pulse0_carry_i_2_n_0 : STD_LOGIC;
  signal out_pulse0_carry_i_3_n_0 : STD_LOGIC;
  signal out_pulse0_carry_i_4_n_0 : STD_LOGIC;
  signal out_pulse0_carry_i_5_n_0 : STD_LOGIC;
  signal out_pulse0_carry_i_6_n_0 : STD_LOGIC;
  signal out_pulse0_carry_i_7_n_0 : STD_LOGIC;
  signal out_pulse0_carry_i_8_n_0 : STD_LOGIC;
  signal out_pulse0_carry_i_9_n_0 : STD_LOGIC;
  signal out_pulse0_carry_n_1 : STD_LOGIC;
  signal out_pulse0_carry_n_2 : STD_LOGIC;
  signal out_pulse0_carry_n_3 : STD_LOGIC;
  signal plusOp0_in : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal toggle : STD_LOGIC;
  signal toggle_i_1_n_0 : STD_LOGIC;
  signal NLW_current_mode0_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_out_pulse0_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \counter[0]_i_1\ : label is "soft_lutpair9";
  attribute SOFT_HLUTNM of \counter[1]_i_1\ : label is "soft_lutpair9";
  attribute SOFT_HLUTNM of \counter[2]_i_1\ : label is "soft_lutpair5";
  attribute SOFT_HLUTNM of \counter[3]_i_1\ : label is "soft_lutpair0";
  attribute SOFT_HLUTNM of \counter[4]_i_1\ : label is "soft_lutpair0";
  attribute SOFT_HLUTNM of \counter[6]_i_1\ : label is "soft_lutpair6";
  attribute SOFT_HLUTNM of \counter[7]_i_1\ : label is "soft_lutpair6";
  attribute SOFT_HLUTNM of \counter[8]_i_1\ : label is "soft_lutpair1";
  attribute SOFT_HLUTNM of \counter[9]_i_1\ : label is "soft_lutpair1";
  attribute SOFT_HLUTNM of \current_limit[1]_i_1\ : label is "soft_lutpair7";
  attribute SOFT_HLUTNM of \current_limit[2]_i_1\ : label is "soft_lutpair3";
  attribute SOFT_HLUTNM of \current_limit[3]_i_1\ : label is "soft_lutpair3";
  attribute SOFT_HLUTNM of \current_limit[5]_i_1\ : label is "soft_lutpair8";
  attribute SOFT_HLUTNM of \current_limit[6]_i_1\ : label is "soft_lutpair8";
  attribute SOFT_HLUTNM of \current_limit[7]_i_1\ : label is "soft_lutpair4";
  attribute SOFT_HLUTNM of \current_limit[8]_i_1\ : label is "soft_lutpair4";
  attribute SOFT_HLUTNM of out_pulse0_carry_i_10 : label is "soft_lutpair2";
  attribute SOFT_HLUTNM of out_pulse0_carry_i_8 : label is "soft_lutpair2";
  attribute SOFT_HLUTNM of out_pulse0_carry_i_9 : label is "soft_lutpair5";
  attribute SOFT_HLUTNM of toggle_i_1 : label is "soft_lutpair7";
begin
\base_n_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => count_val(0),
      Q => base_n(0),
      R => '0'
    );
\base_n_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => count_val(1),
      Q => base_n(1),
      R => '0'
    );
\base_n_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => count_val(2),
      Q => base_n(2),
      R => '0'
    );
\base_n_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => count_val(3),
      Q => base_n(3),
      R => '0'
    );
\base_n_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => count_val(4),
      Q => base_n(4),
      R => '0'
    );
\base_n_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => count_val(5),
      Q => base_n(5),
      R => '0'
    );
\base_n_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => count_val(6),
      Q => base_n(6),
      R => '0'
    );
\base_n_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => count_val(7),
      Q => base_n(7),
      R => '0'
    );
\counter[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => counter_reg(0),
      O => plusOp0_in(0)
    );
\counter[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => counter_reg(0),
      I1 => counter_reg(1),
      O => plusOp0_in(1)
    );
\counter[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => counter_reg(1),
      I1 => counter_reg(0),
      I2 => counter_reg(2),
      O => plusOp0_in(2)
    );
\counter[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => counter_reg(0),
      I1 => counter_reg(1),
      I2 => counter_reg(2),
      I3 => counter_reg(3),
      O => plusOp0_in(3)
    );
\counter[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => counter_reg(3),
      I1 => counter_reg(2),
      I2 => counter_reg(1),
      I3 => counter_reg(0),
      I4 => counter_reg(4),
      O => plusOp0_in(4)
    );
\counter[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFF80000000"
    )
        port map (
      I0 => counter_reg(0),
      I1 => counter_reg(1),
      I2 => counter_reg(2),
      I3 => counter_reg(3),
      I4 => counter_reg(4),
      I5 => counter_reg(5),
      O => plusOp0_in(5)
    );
\counter[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \counter[9]_i_2_n_0\,
      I1 => counter_reg(6),
      O => plusOp0_in(6)
    );
\counter[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => \counter[9]_i_2_n_0\,
      I1 => counter_reg(6),
      I2 => counter_reg(7),
      O => plusOp0_in(7)
    );
\counter[8]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F708"
    )
        port map (
      I0 => counter_reg(7),
      I1 => counter_reg(6),
      I2 => \counter[9]_i_2_n_0\,
      I3 => counter_reg(8),
      O => plusOp0_in(8)
    );
\counter[9]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"DFFF2000"
    )
        port map (
      I0 => counter_reg(8),
      I1 => \counter[9]_i_2_n_0\,
      I2 => counter_reg(6),
      I3 => counter_reg(7),
      I4 => counter_reg(9),
      O => plusOp0_in(9)
    );
\counter[9]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFFFFFFFFFF"
    )
        port map (
      I0 => counter_reg(0),
      I1 => counter_reg(1),
      I2 => counter_reg(2),
      I3 => counter_reg(3),
      I4 => counter_reg(4),
      I5 => counter_reg(5),
      O => \counter[9]_i_2_n_0\
    );
\counter_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => plusOp0_in(0),
      Q => counter_reg(0),
      R => out_pulse0
    );
\counter_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => plusOp0_in(1),
      Q => counter_reg(1),
      R => out_pulse0
    );
\counter_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => plusOp0_in(2),
      Q => counter_reg(2),
      R => out_pulse0
    );
\counter_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => plusOp0_in(3),
      Q => counter_reg(3),
      R => out_pulse0
    );
\counter_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => plusOp0_in(4),
      Q => counter_reg(4),
      R => out_pulse0
    );
\counter_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => plusOp0_in(5),
      Q => counter_reg(5),
      R => out_pulse0
    );
\counter_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => plusOp0_in(6),
      Q => counter_reg(6),
      R => out_pulse0
    );
\counter_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => plusOp0_in(7),
      Q => counter_reg(7),
      R => out_pulse0
    );
\counter_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => plusOp0_in(8),
      Q => counter_reg(8),
      R => out_pulse0
    );
\counter_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => plusOp0_in(9),
      Q => counter_reg(9),
      R => out_pulse0
    );
\current_limit[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => current_mode,
      I1 => toggle,
      I2 => base_n(1),
      O => current_limit(1)
    );
\current_limit[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => toggle,
      I1 => current_mode,
      I2 => base_n(1),
      I3 => base_n(2),
      O => current_limit(2)
    );
\current_limit[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => base_n(1),
      I1 => current_mode,
      I2 => toggle,
      I3 => base_n(2),
      I4 => base_n(3),
      O => current_limit(3)
    );
\current_limit[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFF80000000"
    )
        port map (
      I0 => base_n(2),
      I1 => toggle,
      I2 => current_mode,
      I3 => base_n(1),
      I4 => base_n(3),
      I5 => base_n(4),
      O => current_limit(4)
    );
\current_limit[5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \current_limit[8]_i_2_n_0\,
      I1 => base_n(5),
      O => current_limit(5)
    );
\current_limit[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => \current_limit[8]_i_2_n_0\,
      I1 => base_n(5),
      I2 => base_n(6),
      O => current_limit(6)
    );
\current_limit[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"DF20"
    )
        port map (
      I0 => base_n(5),
      I1 => \current_limit[8]_i_2_n_0\,
      I2 => base_n(6),
      I3 => base_n(7),
      O => current_limit(7)
    );
\current_limit[8]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0800"
    )
        port map (
      I0 => base_n(7),
      I1 => base_n(5),
      I2 => \current_limit[8]_i_2_n_0\,
      I3 => base_n(6),
      O => current_limit(8)
    );
\current_limit[8]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFFFFFFFFFF"
    )
        port map (
      I0 => base_n(4),
      I1 => base_n(2),
      I2 => toggle,
      I3 => current_mode,
      I4 => base_n(1),
      I5 => base_n(3),
      O => \current_limit[8]_i_2_n_0\
    );
\current_limit_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => base_n(0),
      Q => \current_limit_reg_n_0_[0]\,
      R => '0'
    );
\current_limit_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => current_limit(1),
      Q => \current_limit_reg_n_0_[1]\,
      R => '0'
    );
\current_limit_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => current_limit(2),
      Q => \current_limit_reg_n_0_[2]\,
      R => '0'
    );
\current_limit_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => current_limit(3),
      Q => \current_limit_reg_n_0_[3]\,
      R => '0'
    );
\current_limit_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => current_limit(4),
      Q => \current_limit_reg_n_0_[4]\,
      R => '0'
    );
\current_limit_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => current_limit(5),
      Q => \current_limit_reg_n_0_[5]\,
      R => '0'
    );
\current_limit_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => current_limit(6),
      Q => \current_limit_reg_n_0_[6]\,
      R => '0'
    );
\current_limit_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => current_limit(7),
      Q => \current_limit_reg_n_0_[7]\,
      R => '0'
    );
\current_limit_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => current_limit(8),
      Q => \current_limit_reg_n_0_[8]\,
      R => '0'
    );
current_mode0_carry: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => current_mode0,
      CO(2) => current_mode0_carry_n_1,
      CO(1) => current_mode0_carry_n_2,
      CO(0) => current_mode0_carry_n_3,
      CYINIT => '1',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => NLW_current_mode0_carry_O_UNCONNECTED(3 downto 0),
      S(3) => current_mode0_carry_i_1_n_0,
      S(2) => current_mode0_carry_i_2_n_0,
      S(1) => current_mode0_carry_i_3_n_0,
      S(0) => current_mode0_carry_i_4_n_0
    );
current_mode0_carry_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => counter_reg(9),
      O => current_mode0_carry_i_1_n_0
    );
current_mode0_carry_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => counter_reg(7),
      I1 => \current_limit_reg_n_0_[7]\,
      I2 => counter_reg(6),
      I3 => \current_limit_reg_n_0_[6]\,
      I4 => \current_limit_reg_n_0_[8]\,
      I5 => counter_reg(8),
      O => current_mode0_carry_i_2_n_0
    );
current_mode0_carry_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => counter_reg(4),
      I1 => \current_limit_reg_n_0_[4]\,
      I2 => counter_reg(3),
      I3 => \current_limit_reg_n_0_[3]\,
      I4 => \current_limit_reg_n_0_[5]\,
      I5 => counter_reg(5),
      O => current_mode0_carry_i_3_n_0
    );
current_mode0_carry_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => counter_reg(1),
      I1 => \current_limit_reg_n_0_[1]\,
      I2 => counter_reg(2),
      I3 => \current_limit_reg_n_0_[2]\,
      I4 => \current_limit_reg_n_0_[0]\,
      I5 => counter_reg(0),
      O => current_mode0_carry_i_4_n_0
    );
current_mode_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => next_mode,
      I1 => current_mode0,
      I2 => current_mode,
      O => current_mode_i_1_n_0
    );
current_mode_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => current_mode_i_1_n_0,
      Q => current_mode,
      R => '0'
    );
next_mode_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => select_bit,
      Q => next_mode,
      R => '0'
    );
out_pulse0_carry: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => out_pulse0,
      CO(2) => out_pulse0_carry_n_1,
      CO(1) => out_pulse0_carry_n_2,
      CO(0) => out_pulse0_carry_n_3,
      CYINIT => '1',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => NLW_out_pulse0_carry_O_UNCONNECTED(3 downto 0),
      S(3) => out_pulse0_carry_i_1_n_0,
      S(2) => out_pulse0_carry_i_2_n_0,
      S(1) => out_pulse0_carry_i_3_n_0,
      S(0) => out_pulse0_carry_i_4_n_0
    );
out_pulse0_carry_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2000DFFF"
    )
        port map (
      I0 => \current_limit_reg_n_0_[8]\,
      I1 => out_pulse0_carry_i_5_n_0,
      I2 => \current_limit_reg_n_0_[6]\,
      I3 => \current_limit_reg_n_0_[7]\,
      I4 => plusOp0_in(9),
      O => out_pulse0_carry_i_1_n_0
    );
out_pulse0_carry_i_10: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \current_limit_reg_n_0_[2]\,
      I1 => \current_limit_reg_n_0_[1]\,
      I2 => \current_limit_reg_n_0_[0]\,
      O => out_pulse0_carry_i_10_n_0
    );
out_pulse0_carry_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8888288822228222"
    )
        port map (
      I0 => out_pulse0_carry_i_6_n_0,
      I1 => plusOp0_in(8),
      I2 => \current_limit_reg_n_0_[7]\,
      I3 => \current_limit_reg_n_0_[6]\,
      I4 => out_pulse0_carry_i_5_n_0,
      I5 => \current_limit_reg_n_0_[8]\,
      O => out_pulse0_carry_i_2_n_0
    );
out_pulse0_carry_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2882"
    )
        port map (
      I0 => out_pulse0_carry_i_7_n_0,
      I1 => plusOp0_in(5),
      I2 => \current_limit_reg_n_0_[5]\,
      I3 => out_pulse0_carry_i_8_n_0,
      O => out_pulse0_carry_i_3_n_0
    );
out_pulse0_carry_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8040201008040201"
    )
        port map (
      I0 => counter_reg(1),
      I1 => counter_reg(0),
      I2 => counter_reg(2),
      I3 => \current_limit_reg_n_0_[1]\,
      I4 => \current_limit_reg_n_0_[0]\,
      I5 => \current_limit_reg_n_0_[2]\,
      O => out_pulse0_carry_i_4_n_0
    );
out_pulse0_carry_i_5: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFFFFFFFFFF"
    )
        port map (
      I0 => \current_limit_reg_n_0_[0]\,
      I1 => \current_limit_reg_n_0_[1]\,
      I2 => \current_limit_reg_n_0_[2]\,
      I3 => \current_limit_reg_n_0_[3]\,
      I4 => \current_limit_reg_n_0_[4]\,
      I5 => \current_limit_reg_n_0_[5]\,
      O => out_pulse0_carry_i_5_n_0
    );
out_pulse0_carry_i_6: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009096006909009"
    )
        port map (
      I0 => counter_reg(7),
      I1 => \current_limit_reg_n_0_[7]\,
      I2 => \counter[9]_i_2_n_0\,
      I3 => counter_reg(6),
      I4 => out_pulse0_carry_i_5_n_0,
      I5 => \current_limit_reg_n_0_[6]\,
      O => out_pulse0_carry_i_6_n_0
    );
out_pulse0_carry_i_7: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8160601818060681"
    )
        port map (
      I0 => counter_reg(3),
      I1 => out_pulse0_carry_i_9_n_0,
      I2 => counter_reg(4),
      I3 => \current_limit_reg_n_0_[3]\,
      I4 => out_pulse0_carry_i_10_n_0,
      I5 => \current_limit_reg_n_0_[4]\,
      O => out_pulse0_carry_i_7_n_0
    );
out_pulse0_carry_i_8: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \current_limit_reg_n_0_[4]\,
      I1 => \current_limit_reg_n_0_[3]\,
      I2 => \current_limit_reg_n_0_[2]\,
      I3 => \current_limit_reg_n_0_[1]\,
      I4 => \current_limit_reg_n_0_[0]\,
      O => out_pulse0_carry_i_8_n_0
    );
out_pulse0_carry_i_9: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => counter_reg(2),
      I1 => counter_reg(1),
      I2 => counter_reg(0),
      O => out_pulse0_carry_i_9_n_0
    );
out_pulse_reg: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => out_pulse0,
      Q => out_pulse,
      R => '0'
    );
toggle_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => current_mode,
      I1 => out_pulse0,
      I2 => toggle,
      O => toggle_i_1_n_0
    );
toggle_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => toggle_i_1_n_0,
      Q => toggle,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity FNPLL_nn2_div_0_0 is
  port (
    clk : in STD_LOGIC;
    select_bit : in STD_LOGIC;
    count_val : in STD_LOGIC_VECTOR ( 7 downto 0 );
    out_pulse : out STD_LOGIC
  );
  attribute NotValidForBitStream : boolean;
  attribute NotValidForBitStream of FNPLL_nn2_div_0_0 : entity is true;
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of FNPLL_nn2_div_0_0 : entity is "FNPLL_nn2_div_0_0,nn2_div,{}";
  attribute downgradeipidentifiedwarnings : string;
  attribute downgradeipidentifiedwarnings of FNPLL_nn2_div_0_0 : entity is "yes";
  attribute ip_definition_source : string;
  attribute ip_definition_source of FNPLL_nn2_div_0_0 : entity is "module_ref";
  attribute x_core_info : string;
  attribute x_core_info of FNPLL_nn2_div_0_0 : entity is "nn2_div,Vivado 2025.1";
end FNPLL_nn2_div_0_0;

architecture STRUCTURE of FNPLL_nn2_div_0_0 is
  attribute x_interface_info : string;
  attribute x_interface_info of clk : signal is "xilinx.com:signal:clock:1.0 clk CLK";
  attribute x_interface_mode : string;
  attribute x_interface_mode of clk : signal is "slave clk";
  attribute x_interface_parameter : string;
  attribute x_interface_parameter of clk : signal is "XIL_INTERFACENAME clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
begin
U0: entity work.FNPLL_nn2_div_0_0_nn2_div
     port map (
      clk => clk,
      count_val(7 downto 0) => count_val(7 downto 0),
      out_pulse => out_pulse,
      select_bit => select_bit
    );
end STRUCTURE;
