-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2025.1 (win64) Build 6140274 Thu May 22 00:12:29 MDT 2025
-- Date        : Sat Dec 20 08:46:34 2025
-- Host        : LAPTOP-L3CRKKNJ running 64-bit major release  (build 9200)
-- Command     : write_vhdl -force -mode funcsim
--               c:/Vivado_Debug/FNPLL7/FNPLL2.gen/sources_1/bd/FNPLL/ip/FNPLL_digital_loop_filter_0_0/FNPLL_digital_loop_filter_0_0_sim_netlist.vhdl
-- Design      : FNPLL_digital_loop_filter_0_0
-- Purpose     : This VHDL netlist is a functional simulation representation of the design and should not be modified or
--               synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device      : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity FNPLL_digital_loop_filter_0_0_digital_loop_filter is
  port (
    ctrl_out : out STD_LOGIC_VECTOR ( 15 downto 0 );
    rst_n : in STD_LOGIC;
    clk : in STD_LOGIC;
    pfd_dn : in STD_LOGIC;
    pfd_up : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of FNPLL_digital_loop_filter_0_0_digital_loop_filter : entity is "digital_loop_filter";
end FNPLL_digital_loop_filter_0_0_digital_loop_filter;

architecture STRUCTURE of FNPLL_digital_loop_filter_0_0_digital_loop_filter is
  signal \integrator[0]_i_2_n_0\ : STD_LOGIC;
  signal \integrator[0]_i_3_n_0\ : STD_LOGIC;
  signal \integrator[0]_i_4_n_0\ : STD_LOGIC;
  signal \integrator[0]_i_5_n_0\ : STD_LOGIC;
  signal \integrator[12]_i_2_n_0\ : STD_LOGIC;
  signal \integrator[12]_i_3_n_0\ : STD_LOGIC;
  signal \integrator[12]_i_4_n_0\ : STD_LOGIC;
  signal \integrator[12]_i_5_n_0\ : STD_LOGIC;
  signal \integrator[16]_i_2_n_0\ : STD_LOGIC;
  signal \integrator[16]_i_3_n_0\ : STD_LOGIC;
  signal \integrator[16]_i_4_n_0\ : STD_LOGIC;
  signal \integrator[16]_i_5_n_0\ : STD_LOGIC;
  signal \integrator[20]_i_2_n_0\ : STD_LOGIC;
  signal \integrator[20]_i_3_n_0\ : STD_LOGIC;
  signal \integrator[20]_i_4_n_0\ : STD_LOGIC;
  signal \integrator[20]_i_5_n_0\ : STD_LOGIC;
  signal \integrator[24]_i_2_n_0\ : STD_LOGIC;
  signal \integrator[24]_i_3_n_0\ : STD_LOGIC;
  signal \integrator[24]_i_4_n_0\ : STD_LOGIC;
  signal \integrator[24]_i_5_n_0\ : STD_LOGIC;
  signal \integrator[28]_i_2_n_0\ : STD_LOGIC;
  signal \integrator[28]_i_3_n_0\ : STD_LOGIC;
  signal \integrator[28]_i_4_n_0\ : STD_LOGIC;
  signal \integrator[28]_i_5_n_0\ : STD_LOGIC;
  signal \integrator[4]_i_2_n_0\ : STD_LOGIC;
  signal \integrator[4]_i_3_n_0\ : STD_LOGIC;
  signal \integrator[4]_i_4_n_0\ : STD_LOGIC;
  signal \integrator[4]_i_5_n_0\ : STD_LOGIC;
  signal \integrator[8]_i_2_n_0\ : STD_LOGIC;
  signal \integrator[8]_i_3_n_0\ : STD_LOGIC;
  signal \integrator[8]_i_4_n_0\ : STD_LOGIC;
  signal \integrator[8]_i_5_n_0\ : STD_LOGIC;
  signal integrator_reg : STD_LOGIC_VECTOR ( 31 downto 16 );
  signal \integrator_reg[0]_i_1_n_0\ : STD_LOGIC;
  signal \integrator_reg[0]_i_1_n_1\ : STD_LOGIC;
  signal \integrator_reg[0]_i_1_n_2\ : STD_LOGIC;
  signal \integrator_reg[0]_i_1_n_3\ : STD_LOGIC;
  signal \integrator_reg[0]_i_1_n_4\ : STD_LOGIC;
  signal \integrator_reg[0]_i_1_n_5\ : STD_LOGIC;
  signal \integrator_reg[0]_i_1_n_6\ : STD_LOGIC;
  signal \integrator_reg[0]_i_1_n_7\ : STD_LOGIC;
  signal \integrator_reg[12]_i_1_n_0\ : STD_LOGIC;
  signal \integrator_reg[12]_i_1_n_1\ : STD_LOGIC;
  signal \integrator_reg[12]_i_1_n_2\ : STD_LOGIC;
  signal \integrator_reg[12]_i_1_n_3\ : STD_LOGIC;
  signal \integrator_reg[12]_i_1_n_4\ : STD_LOGIC;
  signal \integrator_reg[12]_i_1_n_5\ : STD_LOGIC;
  signal \integrator_reg[12]_i_1_n_6\ : STD_LOGIC;
  signal \integrator_reg[12]_i_1_n_7\ : STD_LOGIC;
  signal \integrator_reg[16]_i_1_n_0\ : STD_LOGIC;
  signal \integrator_reg[16]_i_1_n_1\ : STD_LOGIC;
  signal \integrator_reg[16]_i_1_n_2\ : STD_LOGIC;
  signal \integrator_reg[16]_i_1_n_3\ : STD_LOGIC;
  signal \integrator_reg[16]_i_1_n_4\ : STD_LOGIC;
  signal \integrator_reg[16]_i_1_n_5\ : STD_LOGIC;
  signal \integrator_reg[16]_i_1_n_6\ : STD_LOGIC;
  signal \integrator_reg[16]_i_1_n_7\ : STD_LOGIC;
  signal \integrator_reg[20]_i_1_n_0\ : STD_LOGIC;
  signal \integrator_reg[20]_i_1_n_1\ : STD_LOGIC;
  signal \integrator_reg[20]_i_1_n_2\ : STD_LOGIC;
  signal \integrator_reg[20]_i_1_n_3\ : STD_LOGIC;
  signal \integrator_reg[20]_i_1_n_4\ : STD_LOGIC;
  signal \integrator_reg[20]_i_1_n_5\ : STD_LOGIC;
  signal \integrator_reg[20]_i_1_n_6\ : STD_LOGIC;
  signal \integrator_reg[20]_i_1_n_7\ : STD_LOGIC;
  signal \integrator_reg[24]_i_1_n_0\ : STD_LOGIC;
  signal \integrator_reg[24]_i_1_n_1\ : STD_LOGIC;
  signal \integrator_reg[24]_i_1_n_2\ : STD_LOGIC;
  signal \integrator_reg[24]_i_1_n_3\ : STD_LOGIC;
  signal \integrator_reg[24]_i_1_n_4\ : STD_LOGIC;
  signal \integrator_reg[24]_i_1_n_5\ : STD_LOGIC;
  signal \integrator_reg[24]_i_1_n_6\ : STD_LOGIC;
  signal \integrator_reg[24]_i_1_n_7\ : STD_LOGIC;
  signal \integrator_reg[28]_i_1_n_1\ : STD_LOGIC;
  signal \integrator_reg[28]_i_1_n_2\ : STD_LOGIC;
  signal \integrator_reg[28]_i_1_n_3\ : STD_LOGIC;
  signal \integrator_reg[28]_i_1_n_4\ : STD_LOGIC;
  signal \integrator_reg[28]_i_1_n_5\ : STD_LOGIC;
  signal \integrator_reg[28]_i_1_n_6\ : STD_LOGIC;
  signal \integrator_reg[28]_i_1_n_7\ : STD_LOGIC;
  signal \integrator_reg[4]_i_1_n_0\ : STD_LOGIC;
  signal \integrator_reg[4]_i_1_n_1\ : STD_LOGIC;
  signal \integrator_reg[4]_i_1_n_2\ : STD_LOGIC;
  signal \integrator_reg[4]_i_1_n_3\ : STD_LOGIC;
  signal \integrator_reg[4]_i_1_n_4\ : STD_LOGIC;
  signal \integrator_reg[4]_i_1_n_5\ : STD_LOGIC;
  signal \integrator_reg[4]_i_1_n_6\ : STD_LOGIC;
  signal \integrator_reg[4]_i_1_n_7\ : STD_LOGIC;
  signal \integrator_reg[8]_i_1_n_0\ : STD_LOGIC;
  signal \integrator_reg[8]_i_1_n_1\ : STD_LOGIC;
  signal \integrator_reg[8]_i_1_n_2\ : STD_LOGIC;
  signal \integrator_reg[8]_i_1_n_3\ : STD_LOGIC;
  signal \integrator_reg[8]_i_1_n_4\ : STD_LOGIC;
  signal \integrator_reg[8]_i_1_n_5\ : STD_LOGIC;
  signal \integrator_reg[8]_i_1_n_6\ : STD_LOGIC;
  signal \integrator_reg[8]_i_1_n_7\ : STD_LOGIC;
  signal \integrator_reg_n_0_[0]\ : STD_LOGIC;
  signal \integrator_reg_n_0_[10]\ : STD_LOGIC;
  signal \integrator_reg_n_0_[11]\ : STD_LOGIC;
  signal \integrator_reg_n_0_[12]\ : STD_LOGIC;
  signal \integrator_reg_n_0_[13]\ : STD_LOGIC;
  signal \integrator_reg_n_0_[14]\ : STD_LOGIC;
  signal \integrator_reg_n_0_[15]\ : STD_LOGIC;
  signal \integrator_reg_n_0_[1]\ : STD_LOGIC;
  signal \integrator_reg_n_0_[2]\ : STD_LOGIC;
  signal \integrator_reg_n_0_[3]\ : STD_LOGIC;
  signal \integrator_reg_n_0_[4]\ : STD_LOGIC;
  signal \integrator_reg_n_0_[5]\ : STD_LOGIC;
  signal \integrator_reg_n_0_[6]\ : STD_LOGIC;
  signal \integrator_reg_n_0_[7]\ : STD_LOGIC;
  signal \integrator_reg_n_0_[8]\ : STD_LOGIC;
  signal \integrator_reg_n_0_[9]\ : STD_LOGIC;
  signal \NLW_integrator_reg[28]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  attribute ADDER_THRESHOLD : integer;
  attribute ADDER_THRESHOLD of \integrator_reg[0]_i_1\ : label is 11;
  attribute ADDER_THRESHOLD of \integrator_reg[12]_i_1\ : label is 11;
  attribute ADDER_THRESHOLD of \integrator_reg[16]_i_1\ : label is 11;
  attribute ADDER_THRESHOLD of \integrator_reg[20]_i_1\ : label is 11;
  attribute ADDER_THRESHOLD of \integrator_reg[24]_i_1\ : label is 11;
  attribute ADDER_THRESHOLD of \integrator_reg[28]_i_1\ : label is 11;
  attribute ADDER_THRESHOLD of \integrator_reg[4]_i_1\ : label is 11;
  attribute ADDER_THRESHOLD of \integrator_reg[8]_i_1\ : label is 11;
begin
\integrator[0]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => pfd_up,
      I1 => pfd_dn,
      I2 => \integrator_reg_n_0_[3]\,
      O => \integrator[0]_i_2_n_0\
    );
\integrator[0]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => pfd_up,
      I1 => pfd_dn,
      I2 => \integrator_reg_n_0_[2]\,
      O => \integrator[0]_i_3_n_0\
    );
\integrator[0]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => pfd_up,
      I1 => pfd_dn,
      I2 => \integrator_reg_n_0_[1]\,
      O => \integrator[0]_i_4_n_0\
    );
\integrator[0]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => pfd_dn,
      I1 => pfd_up,
      I2 => \integrator_reg_n_0_[0]\,
      O => \integrator[0]_i_5_n_0\
    );
\integrator[12]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => pfd_up,
      I1 => pfd_dn,
      I2 => \integrator_reg_n_0_[15]\,
      O => \integrator[12]_i_2_n_0\
    );
\integrator[12]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => pfd_up,
      I1 => pfd_dn,
      I2 => \integrator_reg_n_0_[14]\,
      O => \integrator[12]_i_3_n_0\
    );
\integrator[12]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => pfd_up,
      I1 => pfd_dn,
      I2 => \integrator_reg_n_0_[13]\,
      O => \integrator[12]_i_4_n_0\
    );
\integrator[12]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => pfd_up,
      I1 => pfd_dn,
      I2 => \integrator_reg_n_0_[12]\,
      O => \integrator[12]_i_5_n_0\
    );
\integrator[16]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => pfd_up,
      I1 => pfd_dn,
      I2 => integrator_reg(19),
      O => \integrator[16]_i_2_n_0\
    );
\integrator[16]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => pfd_up,
      I1 => pfd_dn,
      I2 => integrator_reg(18),
      O => \integrator[16]_i_3_n_0\
    );
\integrator[16]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => pfd_up,
      I1 => pfd_dn,
      I2 => integrator_reg(17),
      O => \integrator[16]_i_4_n_0\
    );
\integrator[16]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => pfd_up,
      I1 => pfd_dn,
      I2 => integrator_reg(16),
      O => \integrator[16]_i_5_n_0\
    );
\integrator[20]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => pfd_up,
      I1 => pfd_dn,
      I2 => integrator_reg(23),
      O => \integrator[20]_i_2_n_0\
    );
\integrator[20]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => pfd_up,
      I1 => pfd_dn,
      I2 => integrator_reg(22),
      O => \integrator[20]_i_3_n_0\
    );
\integrator[20]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => pfd_up,
      I1 => pfd_dn,
      I2 => integrator_reg(21),
      O => \integrator[20]_i_4_n_0\
    );
\integrator[20]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => pfd_up,
      I1 => pfd_dn,
      I2 => integrator_reg(20),
      O => \integrator[20]_i_5_n_0\
    );
\integrator[24]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => pfd_up,
      I1 => pfd_dn,
      I2 => integrator_reg(27),
      O => \integrator[24]_i_2_n_0\
    );
\integrator[24]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => pfd_up,
      I1 => pfd_dn,
      I2 => integrator_reg(26),
      O => \integrator[24]_i_3_n_0\
    );
\integrator[24]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => pfd_up,
      I1 => pfd_dn,
      I2 => integrator_reg(25),
      O => \integrator[24]_i_4_n_0\
    );
\integrator[24]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => pfd_up,
      I1 => pfd_dn,
      I2 => integrator_reg(24),
      O => \integrator[24]_i_5_n_0\
    );
\integrator[28]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => pfd_up,
      I1 => pfd_dn,
      I2 => integrator_reg(31),
      O => \integrator[28]_i_2_n_0\
    );
\integrator[28]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => pfd_up,
      I1 => pfd_dn,
      I2 => integrator_reg(30),
      O => \integrator[28]_i_3_n_0\
    );
\integrator[28]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => pfd_up,
      I1 => pfd_dn,
      I2 => integrator_reg(29),
      O => \integrator[28]_i_4_n_0\
    );
\integrator[28]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => pfd_up,
      I1 => pfd_dn,
      I2 => integrator_reg(28),
      O => \integrator[28]_i_5_n_0\
    );
\integrator[4]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => pfd_up,
      I1 => pfd_dn,
      I2 => \integrator_reg_n_0_[7]\,
      O => \integrator[4]_i_2_n_0\
    );
\integrator[4]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => pfd_up,
      I1 => pfd_dn,
      I2 => \integrator_reg_n_0_[6]\,
      O => \integrator[4]_i_3_n_0\
    );
\integrator[4]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => pfd_up,
      I1 => pfd_dn,
      I2 => \integrator_reg_n_0_[5]\,
      O => \integrator[4]_i_4_n_0\
    );
\integrator[4]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => pfd_up,
      I1 => pfd_dn,
      I2 => \integrator_reg_n_0_[4]\,
      O => \integrator[4]_i_5_n_0\
    );
\integrator[8]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => pfd_up,
      I1 => pfd_dn,
      I2 => \integrator_reg_n_0_[11]\,
      O => \integrator[8]_i_2_n_0\
    );
\integrator[8]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => pfd_up,
      I1 => pfd_dn,
      I2 => \integrator_reg_n_0_[10]\,
      O => \integrator[8]_i_3_n_0\
    );
\integrator[8]_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => pfd_up,
      I1 => pfd_dn,
      I2 => \integrator_reg_n_0_[9]\,
      O => \integrator[8]_i_4_n_0\
    );
\integrator[8]_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B4"
    )
        port map (
      I0 => pfd_up,
      I1 => pfd_dn,
      I2 => \integrator_reg_n_0_[8]\,
      O => \integrator[8]_i_5_n_0\
    );
\integrator_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \integrator_reg[0]_i_1_n_7\,
      Q => \integrator_reg_n_0_[0]\,
      R => rst_n
    );
\integrator_reg[0]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \integrator_reg[0]_i_1_n_0\,
      CO(2) => \integrator_reg[0]_i_1_n_1\,
      CO(1) => \integrator_reg[0]_i_1_n_2\,
      CO(0) => \integrator_reg[0]_i_1_n_3\,
      CYINIT => '0',
      DI(3) => \integrator_reg_n_0_[3]\,
      DI(2) => \integrator_reg_n_0_[2]\,
      DI(1) => \integrator_reg_n_0_[1]\,
      DI(0) => \integrator_reg_n_0_[0]\,
      O(3) => \integrator_reg[0]_i_1_n_4\,
      O(2) => \integrator_reg[0]_i_1_n_5\,
      O(1) => \integrator_reg[0]_i_1_n_6\,
      O(0) => \integrator_reg[0]_i_1_n_7\,
      S(3) => \integrator[0]_i_2_n_0\,
      S(2) => \integrator[0]_i_3_n_0\,
      S(1) => \integrator[0]_i_4_n_0\,
      S(0) => \integrator[0]_i_5_n_0\
    );
\integrator_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \integrator_reg[8]_i_1_n_5\,
      Q => \integrator_reg_n_0_[10]\,
      R => rst_n
    );
\integrator_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \integrator_reg[8]_i_1_n_4\,
      Q => \integrator_reg_n_0_[11]\,
      R => rst_n
    );
\integrator_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \integrator_reg[12]_i_1_n_7\,
      Q => \integrator_reg_n_0_[12]\,
      R => rst_n
    );
\integrator_reg[12]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \integrator_reg[8]_i_1_n_0\,
      CO(3) => \integrator_reg[12]_i_1_n_0\,
      CO(2) => \integrator_reg[12]_i_1_n_1\,
      CO(1) => \integrator_reg[12]_i_1_n_2\,
      CO(0) => \integrator_reg[12]_i_1_n_3\,
      CYINIT => '0',
      DI(3) => \integrator_reg_n_0_[15]\,
      DI(2) => \integrator_reg_n_0_[14]\,
      DI(1) => \integrator_reg_n_0_[13]\,
      DI(0) => \integrator_reg_n_0_[12]\,
      O(3) => \integrator_reg[12]_i_1_n_4\,
      O(2) => \integrator_reg[12]_i_1_n_5\,
      O(1) => \integrator_reg[12]_i_1_n_6\,
      O(0) => \integrator_reg[12]_i_1_n_7\,
      S(3) => \integrator[12]_i_2_n_0\,
      S(2) => \integrator[12]_i_3_n_0\,
      S(1) => \integrator[12]_i_4_n_0\,
      S(0) => \integrator[12]_i_5_n_0\
    );
\integrator_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \integrator_reg[12]_i_1_n_6\,
      Q => \integrator_reg_n_0_[13]\,
      R => rst_n
    );
\integrator_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \integrator_reg[12]_i_1_n_5\,
      Q => \integrator_reg_n_0_[14]\,
      R => rst_n
    );
\integrator_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \integrator_reg[12]_i_1_n_4\,
      Q => \integrator_reg_n_0_[15]\,
      R => rst_n
    );
\integrator_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \integrator_reg[16]_i_1_n_7\,
      Q => integrator_reg(16),
      R => rst_n
    );
\integrator_reg[16]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \integrator_reg[12]_i_1_n_0\,
      CO(3) => \integrator_reg[16]_i_1_n_0\,
      CO(2) => \integrator_reg[16]_i_1_n_1\,
      CO(1) => \integrator_reg[16]_i_1_n_2\,
      CO(0) => \integrator_reg[16]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => integrator_reg(19 downto 16),
      O(3) => \integrator_reg[16]_i_1_n_4\,
      O(2) => \integrator_reg[16]_i_1_n_5\,
      O(1) => \integrator_reg[16]_i_1_n_6\,
      O(0) => \integrator_reg[16]_i_1_n_7\,
      S(3) => \integrator[16]_i_2_n_0\,
      S(2) => \integrator[16]_i_3_n_0\,
      S(1) => \integrator[16]_i_4_n_0\,
      S(0) => \integrator[16]_i_5_n_0\
    );
\integrator_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \integrator_reg[16]_i_1_n_6\,
      Q => integrator_reg(17),
      R => rst_n
    );
\integrator_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \integrator_reg[16]_i_1_n_5\,
      Q => integrator_reg(18),
      R => rst_n
    );
\integrator_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \integrator_reg[16]_i_1_n_4\,
      Q => integrator_reg(19),
      R => rst_n
    );
\integrator_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \integrator_reg[0]_i_1_n_6\,
      Q => \integrator_reg_n_0_[1]\,
      R => rst_n
    );
\integrator_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \integrator_reg[20]_i_1_n_7\,
      Q => integrator_reg(20),
      R => rst_n
    );
\integrator_reg[20]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \integrator_reg[16]_i_1_n_0\,
      CO(3) => \integrator_reg[20]_i_1_n_0\,
      CO(2) => \integrator_reg[20]_i_1_n_1\,
      CO(1) => \integrator_reg[20]_i_1_n_2\,
      CO(0) => \integrator_reg[20]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => integrator_reg(23 downto 20),
      O(3) => \integrator_reg[20]_i_1_n_4\,
      O(2) => \integrator_reg[20]_i_1_n_5\,
      O(1) => \integrator_reg[20]_i_1_n_6\,
      O(0) => \integrator_reg[20]_i_1_n_7\,
      S(3) => \integrator[20]_i_2_n_0\,
      S(2) => \integrator[20]_i_3_n_0\,
      S(1) => \integrator[20]_i_4_n_0\,
      S(0) => \integrator[20]_i_5_n_0\
    );
\integrator_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \integrator_reg[20]_i_1_n_6\,
      Q => integrator_reg(21),
      R => rst_n
    );
\integrator_reg[22]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \integrator_reg[20]_i_1_n_5\,
      Q => integrator_reg(22),
      R => rst_n
    );
\integrator_reg[23]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \integrator_reg[20]_i_1_n_4\,
      Q => integrator_reg(23),
      R => rst_n
    );
\integrator_reg[24]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \integrator_reg[24]_i_1_n_7\,
      Q => integrator_reg(24),
      R => rst_n
    );
\integrator_reg[24]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \integrator_reg[20]_i_1_n_0\,
      CO(3) => \integrator_reg[24]_i_1_n_0\,
      CO(2) => \integrator_reg[24]_i_1_n_1\,
      CO(1) => \integrator_reg[24]_i_1_n_2\,
      CO(0) => \integrator_reg[24]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => integrator_reg(27 downto 24),
      O(3) => \integrator_reg[24]_i_1_n_4\,
      O(2) => \integrator_reg[24]_i_1_n_5\,
      O(1) => \integrator_reg[24]_i_1_n_6\,
      O(0) => \integrator_reg[24]_i_1_n_7\,
      S(3) => \integrator[24]_i_2_n_0\,
      S(2) => \integrator[24]_i_3_n_0\,
      S(1) => \integrator[24]_i_4_n_0\,
      S(0) => \integrator[24]_i_5_n_0\
    );
\integrator_reg[25]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \integrator_reg[24]_i_1_n_6\,
      Q => integrator_reg(25),
      R => rst_n
    );
\integrator_reg[26]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \integrator_reg[24]_i_1_n_5\,
      Q => integrator_reg(26),
      R => rst_n
    );
\integrator_reg[27]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \integrator_reg[24]_i_1_n_4\,
      Q => integrator_reg(27),
      R => rst_n
    );
\integrator_reg[28]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \integrator_reg[28]_i_1_n_7\,
      Q => integrator_reg(28),
      R => rst_n
    );
\integrator_reg[28]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \integrator_reg[24]_i_1_n_0\,
      CO(3) => \NLW_integrator_reg[28]_i_1_CO_UNCONNECTED\(3),
      CO(2) => \integrator_reg[28]_i_1_n_1\,
      CO(1) => \integrator_reg[28]_i_1_n_2\,
      CO(0) => \integrator_reg[28]_i_1_n_3\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2 downto 0) => integrator_reg(30 downto 28),
      O(3) => \integrator_reg[28]_i_1_n_4\,
      O(2) => \integrator_reg[28]_i_1_n_5\,
      O(1) => \integrator_reg[28]_i_1_n_6\,
      O(0) => \integrator_reg[28]_i_1_n_7\,
      S(3) => \integrator[28]_i_2_n_0\,
      S(2) => \integrator[28]_i_3_n_0\,
      S(1) => \integrator[28]_i_4_n_0\,
      S(0) => \integrator[28]_i_5_n_0\
    );
\integrator_reg[29]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \integrator_reg[28]_i_1_n_6\,
      Q => integrator_reg(29),
      R => rst_n
    );
\integrator_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \integrator_reg[0]_i_1_n_5\,
      Q => \integrator_reg_n_0_[2]\,
      R => rst_n
    );
\integrator_reg[30]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \integrator_reg[28]_i_1_n_5\,
      Q => integrator_reg(30),
      R => rst_n
    );
\integrator_reg[31]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \integrator_reg[28]_i_1_n_4\,
      Q => integrator_reg(31),
      R => rst_n
    );
\integrator_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \integrator_reg[0]_i_1_n_4\,
      Q => \integrator_reg_n_0_[3]\,
      R => rst_n
    );
\integrator_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \integrator_reg[4]_i_1_n_7\,
      Q => \integrator_reg_n_0_[4]\,
      R => rst_n
    );
\integrator_reg[4]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \integrator_reg[0]_i_1_n_0\,
      CO(3) => \integrator_reg[4]_i_1_n_0\,
      CO(2) => \integrator_reg[4]_i_1_n_1\,
      CO(1) => \integrator_reg[4]_i_1_n_2\,
      CO(0) => \integrator_reg[4]_i_1_n_3\,
      CYINIT => '0',
      DI(3) => \integrator_reg_n_0_[7]\,
      DI(2) => \integrator_reg_n_0_[6]\,
      DI(1) => \integrator_reg_n_0_[5]\,
      DI(0) => \integrator_reg_n_0_[4]\,
      O(3) => \integrator_reg[4]_i_1_n_4\,
      O(2) => \integrator_reg[4]_i_1_n_5\,
      O(1) => \integrator_reg[4]_i_1_n_6\,
      O(0) => \integrator_reg[4]_i_1_n_7\,
      S(3) => \integrator[4]_i_2_n_0\,
      S(2) => \integrator[4]_i_3_n_0\,
      S(1) => \integrator[4]_i_4_n_0\,
      S(0) => \integrator[4]_i_5_n_0\
    );
\integrator_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \integrator_reg[4]_i_1_n_6\,
      Q => \integrator_reg_n_0_[5]\,
      R => rst_n
    );
\integrator_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \integrator_reg[4]_i_1_n_5\,
      Q => \integrator_reg_n_0_[6]\,
      R => rst_n
    );
\integrator_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \integrator_reg[4]_i_1_n_4\,
      Q => \integrator_reg_n_0_[7]\,
      R => rst_n
    );
\integrator_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \integrator_reg[8]_i_1_n_7\,
      Q => \integrator_reg_n_0_[8]\,
      R => rst_n
    );
\integrator_reg[8]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \integrator_reg[4]_i_1_n_0\,
      CO(3) => \integrator_reg[8]_i_1_n_0\,
      CO(2) => \integrator_reg[8]_i_1_n_1\,
      CO(1) => \integrator_reg[8]_i_1_n_2\,
      CO(0) => \integrator_reg[8]_i_1_n_3\,
      CYINIT => '0',
      DI(3) => \integrator_reg_n_0_[11]\,
      DI(2) => \integrator_reg_n_0_[10]\,
      DI(1) => \integrator_reg_n_0_[9]\,
      DI(0) => \integrator_reg_n_0_[8]\,
      O(3) => \integrator_reg[8]_i_1_n_4\,
      O(2) => \integrator_reg[8]_i_1_n_5\,
      O(1) => \integrator_reg[8]_i_1_n_6\,
      O(0) => \integrator_reg[8]_i_1_n_7\,
      S(3) => \integrator[8]_i_2_n_0\,
      S(2) => \integrator[8]_i_3_n_0\,
      S(1) => \integrator[8]_i_4_n_0\,
      S(0) => \integrator[8]_i_5_n_0\
    );
\integrator_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \integrator_reg[8]_i_1_n_6\,
      Q => \integrator_reg_n_0_[9]\,
      R => rst_n
    );
\output_reg_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => integrator_reg(16),
      Q => ctrl_out(0),
      R => rst_n
    );
\output_reg_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => integrator_reg(26),
      Q => ctrl_out(10),
      R => rst_n
    );
\output_reg_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => integrator_reg(27),
      Q => ctrl_out(11),
      R => rst_n
    );
\output_reg_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => integrator_reg(28),
      Q => ctrl_out(12),
      R => rst_n
    );
\output_reg_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => integrator_reg(29),
      Q => ctrl_out(13),
      R => rst_n
    );
\output_reg_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => integrator_reg(30),
      Q => ctrl_out(14),
      R => rst_n
    );
\output_reg_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => integrator_reg(31),
      Q => ctrl_out(15),
      R => rst_n
    );
\output_reg_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => integrator_reg(17),
      Q => ctrl_out(1),
      R => rst_n
    );
\output_reg_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => integrator_reg(18),
      Q => ctrl_out(2),
      R => rst_n
    );
\output_reg_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => integrator_reg(19),
      Q => ctrl_out(3),
      R => rst_n
    );
\output_reg_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => integrator_reg(20),
      Q => ctrl_out(4),
      R => rst_n
    );
\output_reg_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => integrator_reg(21),
      Q => ctrl_out(5),
      R => rst_n
    );
\output_reg_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => integrator_reg(22),
      Q => ctrl_out(6),
      R => rst_n
    );
\output_reg_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => integrator_reg(23),
      Q => ctrl_out(7),
      R => rst_n
    );
\output_reg_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => integrator_reg(24),
      Q => ctrl_out(8),
      R => rst_n
    );
\output_reg_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => integrator_reg(25),
      Q => ctrl_out(9),
      R => rst_n
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity FNPLL_digital_loop_filter_0_0 is
  port (
    clk : in STD_LOGIC;
    rst_n : in STD_LOGIC;
    pfd_up : in STD_LOGIC;
    pfd_dn : in STD_LOGIC;
    ctrl_out : out STD_LOGIC_VECTOR ( 15 downto 0 )
  );
  attribute NotValidForBitStream : boolean;
  attribute NotValidForBitStream of FNPLL_digital_loop_filter_0_0 : entity is true;
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of FNPLL_digital_loop_filter_0_0 : entity is "FNPLL_digital_loop_filter_0_0,digital_loop_filter,{}";
  attribute downgradeipidentifiedwarnings : string;
  attribute downgradeipidentifiedwarnings of FNPLL_digital_loop_filter_0_0 : entity is "yes";
  attribute ip_definition_source : string;
  attribute ip_definition_source of FNPLL_digital_loop_filter_0_0 : entity is "module_ref";
  attribute x_core_info : string;
  attribute x_core_info of FNPLL_digital_loop_filter_0_0 : entity is "digital_loop_filter,Vivado 2025.1";
end FNPLL_digital_loop_filter_0_0;

architecture STRUCTURE of FNPLL_digital_loop_filter_0_0 is
  attribute x_interface_info : string;
  attribute x_interface_info of clk : signal is "xilinx.com:signal:clock:1.0 clk CLK";
  attribute x_interface_mode : string;
  attribute x_interface_mode of clk : signal is "slave clk";
  attribute x_interface_parameter : string;
  attribute x_interface_parameter of clk : signal is "XIL_INTERFACENAME clk, FREQ_HZ 300625000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, INSERT_VIP 0";
  attribute x_interface_info of rst_n : signal is "xilinx.com:signal:reset:1.0 rst_n RST";
  attribute x_interface_mode of rst_n : signal is "slave rst_n";
  attribute x_interface_parameter of rst_n : signal is "XIL_INTERFACENAME rst_n, POLARITY ACTIVE_LOW, INSERT_VIP 0";
begin
U0: entity work.FNPLL_digital_loop_filter_0_0_digital_loop_filter
     port map (
      clk => clk,
      ctrl_out(15 downto 0) => ctrl_out(15 downto 0),
      pfd_dn => pfd_dn,
      pfd_up => pfd_up,
      rst_n => rst_n
    );
end STRUCTURE;
