// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2025.1 (win64) Build 6140274 Thu May 22 00:12:29 MDT 2025
// Date        : Sat Dec 20 13:01:00 2025
// Host        : LAPTOP-L3CRKKNJ running 64-bit major release  (build 9200)
// Command     : write_verilog -force -mode funcsim
//               c:/Vivado_Debug/FNPLL8/FNPLL2.gen/sources_1/bd/FNPLL/ip/FNPLL_filt_iir_0_0/FNPLL_filt_iir_0_0_sim_netlist.v
// Design      : FNPLL_filt_iir_0_0
// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
//               or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device      : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

(* CHECK_LICENSE_TYPE = "FNPLL_filt_iir_0_0,filt_iir,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "module_ref" *) 
(* x_core_info = "filt_iir,Vivado 2025.1" *) 
(* NotValidForBitStream *)
module FNPLL_filt_iir_0_0
   (clk,
    reset,
    pulse_in,
    ctrl_out);
  (* x_interface_info = "xilinx.com:signal:clock:1.0 clk CLK" *) (* x_interface_mode = "slave clk" *) (* x_interface_parameter = "XIL_INTERFACENAME clk, ASSOCIATED_RESET reset, FREQ_HZ 300625000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, INSERT_VIP 0" *) input clk;
  (* x_interface_info = "xilinx.com:signal:reset:1.0 reset RST" *) (* x_interface_mode = "slave reset" *) (* x_interface_parameter = "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input reset;
  input pulse_in;
  output [15:0]ctrl_out;

  wire clk;
  wire [15:0]ctrl_out;
  wire pulse_in;
  wire reset;

  FNPLL_filt_iir_0_0_filt_iir U0
       (.clk(clk),
        .ctrl_out(ctrl_out),
        .pulse_in(pulse_in),
        .reset(reset));
endmodule

(* ORIG_REF_NAME = "filt_iir" *) 
module FNPLL_filt_iir_0_0_filt_iir
   (ctrl_out,
    reset,
    pulse_in,
    clk);
  output [15:0]ctrl_out;
  input reset;
  input pulse_in;
  input clk;

  wire ARG_carry__0_i_1_n_0;
  wire ARG_carry__0_i_2_n_0;
  wire ARG_carry__0_i_3_n_0;
  wire ARG_carry__0_i_4_n_0;
  wire ARG_carry__0_n_0;
  wire ARG_carry__0_n_1;
  wire ARG_carry__0_n_2;
  wire ARG_carry__0_n_3;
  wire ARG_carry__1_i_1_n_0;
  wire ARG_carry__1_i_2_n_0;
  wire ARG_carry__1_i_3_n_0;
  wire ARG_carry__1_i_4_n_0;
  wire ARG_carry__1_n_0;
  wire ARG_carry__1_n_1;
  wire ARG_carry__1_n_2;
  wire ARG_carry__1_n_3;
  wire ARG_carry__1_n_4;
  wire ARG_carry__1_n_5;
  wire ARG_carry__2_i_1_n_0;
  wire ARG_carry__2_i_2_n_0;
  wire ARG_carry__2_i_3_n_0;
  wire ARG_carry__2_i_4_n_0;
  wire ARG_carry__2_n_0;
  wire ARG_carry__2_n_1;
  wire ARG_carry__2_n_2;
  wire ARG_carry__2_n_3;
  wire ARG_carry__2_n_4;
  wire ARG_carry__2_n_5;
  wire ARG_carry__2_n_6;
  wire ARG_carry__2_n_7;
  wire ARG_carry__3_i_1_n_0;
  wire ARG_carry__3_i_2_n_0;
  wire ARG_carry__3_i_3_n_0;
  wire ARG_carry__3_i_4_n_0;
  wire ARG_carry__3_n_0;
  wire ARG_carry__3_n_1;
  wire ARG_carry__3_n_2;
  wire ARG_carry__3_n_3;
  wire ARG_carry__3_n_4;
  wire ARG_carry__3_n_5;
  wire ARG_carry__3_n_6;
  wire ARG_carry__3_n_7;
  wire ARG_carry__4_i_1_n_0;
  wire ARG_carry__4_i_2_n_0;
  wire ARG_carry__4_i_3_n_0;
  wire ARG_carry__4_i_4_n_0;
  wire ARG_carry__4_n_0;
  wire ARG_carry__4_n_1;
  wire ARG_carry__4_n_2;
  wire ARG_carry__4_n_3;
  wire ARG_carry__4_n_4;
  wire ARG_carry__4_n_5;
  wire ARG_carry__4_n_6;
  wire ARG_carry__4_n_7;
  wire ARG_carry__5_i_1_n_0;
  wire ARG_carry__5_i_2_n_0;
  wire ARG_carry__5_i_3_n_0;
  wire ARG_carry__5_i_4_n_0;
  wire ARG_carry__5_n_0;
  wire ARG_carry__5_n_1;
  wire ARG_carry__5_n_2;
  wire ARG_carry__5_n_3;
  wire ARG_carry__5_n_4;
  wire ARG_carry__5_n_5;
  wire ARG_carry__5_n_6;
  wire ARG_carry__5_n_7;
  wire ARG_carry__6_i_1_n_0;
  wire ARG_carry__6_i_2_n_0;
  wire ARG_carry__6_i_3_n_0;
  wire ARG_carry__6_i_4_n_0;
  wire ARG_carry__6_n_1;
  wire ARG_carry__6_n_2;
  wire ARG_carry__6_n_3;
  wire ARG_carry__6_n_5;
  wire ARG_carry__6_n_6;
  wire ARG_carry__6_n_7;
  wire ARG_carry_i_1_n_0;
  wire ARG_carry_i_2_n_0;
  wire ARG_carry_i_3_n_0;
  wire ARG_carry_i_4_n_0;
  wire ARG_carry_i_5_n_0;
  wire ARG_carry_n_0;
  wire ARG_carry_n_1;
  wire ARG_carry_n_2;
  wire ARG_carry_n_3;
  wire \accumulator[0]_i_2_n_0 ;
  wire \accumulator[0]_i_3_n_0 ;
  wire \accumulator[0]_i_4_n_0 ;
  wire \accumulator[0]_i_5_n_0 ;
  wire \accumulator[11]_i_2_n_0 ;
  wire \accumulator[11]_i_3_n_0 ;
  wire \accumulator[11]_i_4_n_0 ;
  wire \accumulator[11]_i_5_n_0 ;
  wire \accumulator[15]_i_2_n_0 ;
  wire \accumulator[15]_i_3_n_0 ;
  wire \accumulator[15]_i_4_n_0 ;
  wire \accumulator[15]_i_5_n_0 ;
  wire \accumulator[19]_i_2_n_0 ;
  wire \accumulator[19]_i_3_n_0 ;
  wire \accumulator[19]_i_4_n_0 ;
  wire \accumulator[19]_i_5_n_0 ;
  wire \accumulator[23]_i_2_n_0 ;
  wire \accumulator[23]_i_3_n_0 ;
  wire \accumulator[23]_i_4_n_0 ;
  wire \accumulator[23]_i_5_n_0 ;
  wire \accumulator[25]_i_2_n_0 ;
  wire \accumulator[25]_i_3_n_0 ;
  wire \accumulator[25]_i_4_n_0 ;
  wire \accumulator[25]_i_5_n_0 ;
  wire \accumulator[28]_i_2_n_0 ;
  wire \accumulator[28]_i_3_n_0 ;
  wire \accumulator[28]_i_4_n_0 ;
  wire \accumulator[28]_i_5_n_0 ;
  wire \accumulator[4]_i_2_n_0 ;
  wire \accumulator[4]_i_3_n_0 ;
  wire \accumulator[4]_i_4_n_0 ;
  wire \accumulator[4]_i_5_n_0 ;
  wire [31:0]accumulator_reg;
  wire \accumulator_reg[0]_i_1_n_0 ;
  wire \accumulator_reg[0]_i_1_n_1 ;
  wire \accumulator_reg[0]_i_1_n_2 ;
  wire \accumulator_reg[0]_i_1_n_3 ;
  wire \accumulator_reg[0]_i_1_n_4 ;
  wire \accumulator_reg[0]_i_1_n_5 ;
  wire \accumulator_reg[0]_i_1_n_6 ;
  wire \accumulator_reg[0]_i_1_n_7 ;
  wire \accumulator_reg[11]_i_1_n_0 ;
  wire \accumulator_reg[11]_i_1_n_1 ;
  wire \accumulator_reg[11]_i_1_n_2 ;
  wire \accumulator_reg[11]_i_1_n_3 ;
  wire \accumulator_reg[11]_i_1_n_4 ;
  wire \accumulator_reg[11]_i_1_n_5 ;
  wire \accumulator_reg[11]_i_1_n_6 ;
  wire \accumulator_reg[11]_i_1_n_7 ;
  wire \accumulator_reg[15]_i_1_n_0 ;
  wire \accumulator_reg[15]_i_1_n_1 ;
  wire \accumulator_reg[15]_i_1_n_2 ;
  wire \accumulator_reg[15]_i_1_n_3 ;
  wire \accumulator_reg[15]_i_1_n_4 ;
  wire \accumulator_reg[15]_i_1_n_5 ;
  wire \accumulator_reg[15]_i_1_n_6 ;
  wire \accumulator_reg[15]_i_1_n_7 ;
  wire \accumulator_reg[19]_i_1_n_0 ;
  wire \accumulator_reg[19]_i_1_n_1 ;
  wire \accumulator_reg[19]_i_1_n_2 ;
  wire \accumulator_reg[19]_i_1_n_3 ;
  wire \accumulator_reg[19]_i_1_n_4 ;
  wire \accumulator_reg[19]_i_1_n_5 ;
  wire \accumulator_reg[19]_i_1_n_6 ;
  wire \accumulator_reg[19]_i_1_n_7 ;
  wire \accumulator_reg[23]_i_1_n_0 ;
  wire \accumulator_reg[23]_i_1_n_1 ;
  wire \accumulator_reg[23]_i_1_n_2 ;
  wire \accumulator_reg[23]_i_1_n_3 ;
  wire \accumulator_reg[23]_i_1_n_4 ;
  wire \accumulator_reg[23]_i_1_n_5 ;
  wire \accumulator_reg[23]_i_1_n_6 ;
  wire \accumulator_reg[23]_i_1_n_7 ;
  wire \accumulator_reg[25]_i_1_n_0 ;
  wire \accumulator_reg[25]_i_1_n_1 ;
  wire \accumulator_reg[25]_i_1_n_2 ;
  wire \accumulator_reg[25]_i_1_n_3 ;
  wire \accumulator_reg[25]_i_1_n_4 ;
  wire \accumulator_reg[25]_i_1_n_5 ;
  wire \accumulator_reg[25]_i_1_n_6 ;
  wire \accumulator_reg[25]_i_1_n_7 ;
  wire \accumulator_reg[28]_i_1_n_1 ;
  wire \accumulator_reg[28]_i_1_n_2 ;
  wire \accumulator_reg[28]_i_1_n_3 ;
  wire \accumulator_reg[28]_i_1_n_4 ;
  wire \accumulator_reg[28]_i_1_n_5 ;
  wire \accumulator_reg[28]_i_1_n_6 ;
  wire \accumulator_reg[28]_i_1_n_7 ;
  wire \accumulator_reg[4]_i_1_n_0 ;
  wire \accumulator_reg[4]_i_1_n_1 ;
  wire \accumulator_reg[4]_i_1_n_2 ;
  wire \accumulator_reg[4]_i_1_n_3 ;
  wire \accumulator_reg[4]_i_1_n_4 ;
  wire \accumulator_reg[4]_i_1_n_5 ;
  wire \accumulator_reg[4]_i_1_n_6 ;
  wire \accumulator_reg[4]_i_1_n_7 ;
  wire clk;
  wire [15:0]ctrl_out;
  wire in0;
  wire pulse_in;
  wire pulse_sync1;
  wire pulse_sync2;
  wire reset;
  wire [3:0]NLW_ARG_carry_O_UNCONNECTED;
  wire [3:0]NLW_ARG_carry__0_O_UNCONNECTED;
  wire [1:0]NLW_ARG_carry__1_O_UNCONNECTED;
  wire [3:3]NLW_ARG_carry__6_CO_UNCONNECTED;
  wire [3:3]\NLW_accumulator_reg[28]_i_1_CO_UNCONNECTED ;

  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 ARG_carry
       (.CI(1'b0),
        .CO({ARG_carry_n_0,ARG_carry_n_1,ARG_carry_n_2,ARG_carry_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,ARG_carry_i_1_n_0,1'b0}),
        .O(NLW_ARG_carry_O_UNCONNECTED[3:0]),
        .S({ARG_carry_i_2_n_0,ARG_carry_i_3_n_0,ARG_carry_i_4_n_0,ARG_carry_i_5_n_0}));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 ARG_carry__0
       (.CI(ARG_carry_n_0),
        .CO({ARG_carry__0_n_0,ARG_carry__0_n_1,ARG_carry__0_n_2,ARG_carry__0_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_ARG_carry__0_O_UNCONNECTED[3:0]),
        .S({ARG_carry__0_i_1_n_0,ARG_carry__0_i_2_n_0,ARG_carry__0_i_3_n_0,ARG_carry__0_i_4_n_0}));
  LUT1 #(
    .INIT(2'h1)) 
    ARG_carry__0_i_1
       (.I0(accumulator_reg[7]),
        .O(ARG_carry__0_i_1_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    ARG_carry__0_i_2
       (.I0(accumulator_reg[6]),
        .O(ARG_carry__0_i_2_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    ARG_carry__0_i_3
       (.I0(accumulator_reg[5]),
        .O(ARG_carry__0_i_3_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    ARG_carry__0_i_4
       (.I0(accumulator_reg[4]),
        .O(ARG_carry__0_i_4_n_0));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 ARG_carry__1
       (.CI(ARG_carry__0_n_0),
        .CO({ARG_carry__1_n_0,ARG_carry__1_n_1,ARG_carry__1_n_2,ARG_carry__1_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({ARG_carry__1_n_4,ARG_carry__1_n_5,NLW_ARG_carry__1_O_UNCONNECTED[1:0]}),
        .S({ARG_carry__1_i_1_n_0,ARG_carry__1_i_2_n_0,ARG_carry__1_i_3_n_0,ARG_carry__1_i_4_n_0}));
  LUT1 #(
    .INIT(2'h1)) 
    ARG_carry__1_i_1
       (.I0(ctrl_out[1]),
        .O(ARG_carry__1_i_1_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    ARG_carry__1_i_2
       (.I0(ctrl_out[0]),
        .O(ARG_carry__1_i_2_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    ARG_carry__1_i_3
       (.I0(accumulator_reg[9]),
        .O(ARG_carry__1_i_3_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    ARG_carry__1_i_4
       (.I0(accumulator_reg[8]),
        .O(ARG_carry__1_i_4_n_0));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 ARG_carry__2
       (.CI(ARG_carry__1_n_0),
        .CO({ARG_carry__2_n_0,ARG_carry__2_n_1,ARG_carry__2_n_2,ARG_carry__2_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({ARG_carry__2_n_4,ARG_carry__2_n_5,ARG_carry__2_n_6,ARG_carry__2_n_7}),
        .S({ARG_carry__2_i_1_n_0,ARG_carry__2_i_2_n_0,ARG_carry__2_i_3_n_0,ARG_carry__2_i_4_n_0}));
  LUT1 #(
    .INIT(2'h1)) 
    ARG_carry__2_i_1
       (.I0(ctrl_out[5]),
        .O(ARG_carry__2_i_1_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    ARG_carry__2_i_2
       (.I0(ctrl_out[4]),
        .O(ARG_carry__2_i_2_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    ARG_carry__2_i_3
       (.I0(ctrl_out[3]),
        .O(ARG_carry__2_i_3_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    ARG_carry__2_i_4
       (.I0(ctrl_out[2]),
        .O(ARG_carry__2_i_4_n_0));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 ARG_carry__3
       (.CI(ARG_carry__2_n_0),
        .CO({ARG_carry__3_n_0,ARG_carry__3_n_1,ARG_carry__3_n_2,ARG_carry__3_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({ARG_carry__3_n_4,ARG_carry__3_n_5,ARG_carry__3_n_6,ARG_carry__3_n_7}),
        .S({ARG_carry__3_i_1_n_0,ARG_carry__3_i_2_n_0,ARG_carry__3_i_3_n_0,ARG_carry__3_i_4_n_0}));
  LUT1 #(
    .INIT(2'h1)) 
    ARG_carry__3_i_1
       (.I0(ctrl_out[9]),
        .O(ARG_carry__3_i_1_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    ARG_carry__3_i_2
       (.I0(ctrl_out[8]),
        .O(ARG_carry__3_i_2_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    ARG_carry__3_i_3
       (.I0(ctrl_out[7]),
        .O(ARG_carry__3_i_3_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    ARG_carry__3_i_4
       (.I0(ctrl_out[6]),
        .O(ARG_carry__3_i_4_n_0));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 ARG_carry__4
       (.CI(ARG_carry__3_n_0),
        .CO({ARG_carry__4_n_0,ARG_carry__4_n_1,ARG_carry__4_n_2,ARG_carry__4_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({ARG_carry__4_n_4,ARG_carry__4_n_5,ARG_carry__4_n_6,ARG_carry__4_n_7}),
        .S({ARG_carry__4_i_1_n_0,ARG_carry__4_i_2_n_0,ARG_carry__4_i_3_n_0,ARG_carry__4_i_4_n_0}));
  LUT1 #(
    .INIT(2'h1)) 
    ARG_carry__4_i_1
       (.I0(ctrl_out[13]),
        .O(ARG_carry__4_i_1_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    ARG_carry__4_i_2
       (.I0(ctrl_out[12]),
        .O(ARG_carry__4_i_2_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    ARG_carry__4_i_3
       (.I0(ctrl_out[11]),
        .O(ARG_carry__4_i_3_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    ARG_carry__4_i_4
       (.I0(ctrl_out[10]),
        .O(ARG_carry__4_i_4_n_0));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 ARG_carry__5
       (.CI(ARG_carry__4_n_0),
        .CO({ARG_carry__5_n_0,ARG_carry__5_n_1,ARG_carry__5_n_2,ARG_carry__5_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({ARG_carry__5_n_4,ARG_carry__5_n_5,ARG_carry__5_n_6,ARG_carry__5_n_7}),
        .S({ARG_carry__5_i_1_n_0,ARG_carry__5_i_2_n_0,ARG_carry__5_i_3_n_0,ARG_carry__5_i_4_n_0}));
  LUT1 #(
    .INIT(2'h1)) 
    ARG_carry__5_i_1
       (.I0(accumulator_reg[27]),
        .O(ARG_carry__5_i_1_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    ARG_carry__5_i_2
       (.I0(accumulator_reg[26]),
        .O(ARG_carry__5_i_2_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    ARG_carry__5_i_3
       (.I0(ctrl_out[15]),
        .O(ARG_carry__5_i_3_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    ARG_carry__5_i_4
       (.I0(ctrl_out[14]),
        .O(ARG_carry__5_i_4_n_0));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 ARG_carry__6
       (.CI(ARG_carry__5_n_0),
        .CO({NLW_ARG_carry__6_CO_UNCONNECTED[3],ARG_carry__6_n_1,ARG_carry__6_n_2,ARG_carry__6_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({in0,ARG_carry__6_n_5,ARG_carry__6_n_6,ARG_carry__6_n_7}),
        .S({ARG_carry__6_i_1_n_0,ARG_carry__6_i_2_n_0,ARG_carry__6_i_3_n_0,ARG_carry__6_i_4_n_0}));
  LUT1 #(
    .INIT(2'h1)) 
    ARG_carry__6_i_1
       (.I0(accumulator_reg[31]),
        .O(ARG_carry__6_i_1_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    ARG_carry__6_i_2
       (.I0(accumulator_reg[30]),
        .O(ARG_carry__6_i_2_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    ARG_carry__6_i_3
       (.I0(accumulator_reg[29]),
        .O(ARG_carry__6_i_3_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    ARG_carry__6_i_4
       (.I0(accumulator_reg[28]),
        .O(ARG_carry__6_i_4_n_0));
  LUT2 #(
    .INIT(4'hB)) 
    ARG_carry_i_1
       (.I0(pulse_sync2),
        .I1(accumulator_reg[0]),
        .O(ARG_carry_i_1_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    ARG_carry_i_2
       (.I0(accumulator_reg[3]),
        .O(ARG_carry_i_2_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    ARG_carry_i_3
       (.I0(accumulator_reg[2]),
        .O(ARG_carry_i_3_n_0));
  LUT3 #(
    .INIT(8'hD2)) 
    ARG_carry_i_4
       (.I0(accumulator_reg[0]),
        .I1(pulse_sync2),
        .I2(accumulator_reg[1]),
        .O(ARG_carry_i_4_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    ARG_carry_i_5
       (.I0(pulse_sync2),
        .I1(accumulator_reg[0]),
        .O(ARG_carry_i_5_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    \accumulator[0]_i_2 
       (.I0(ARG_carry__2_n_6),
        .I1(accumulator_reg[3]),
        .O(\accumulator[0]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \accumulator[0]_i_3 
       (.I0(ARG_carry__2_n_7),
        .I1(accumulator_reg[2]),
        .O(\accumulator[0]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \accumulator[0]_i_4 
       (.I0(ARG_carry__1_n_4),
        .I1(accumulator_reg[1]),
        .O(\accumulator[0]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \accumulator[0]_i_5 
       (.I0(ARG_carry__1_n_5),
        .I1(accumulator_reg[0]),
        .O(\accumulator[0]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \accumulator[11]_i_2 
       (.I0(ARG_carry__4_n_6),
        .I1(ctrl_out[1]),
        .O(\accumulator[11]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \accumulator[11]_i_3 
       (.I0(ARG_carry__4_n_7),
        .I1(ctrl_out[0]),
        .O(\accumulator[11]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \accumulator[11]_i_4 
       (.I0(ARG_carry__3_n_4),
        .I1(accumulator_reg[9]),
        .O(\accumulator[11]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \accumulator[11]_i_5 
       (.I0(ARG_carry__3_n_5),
        .I1(accumulator_reg[8]),
        .O(\accumulator[11]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \accumulator[15]_i_2 
       (.I0(ARG_carry__5_n_6),
        .I1(ctrl_out[5]),
        .O(\accumulator[15]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \accumulator[15]_i_3 
       (.I0(ARG_carry__5_n_7),
        .I1(ctrl_out[4]),
        .O(\accumulator[15]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \accumulator[15]_i_4 
       (.I0(ARG_carry__4_n_4),
        .I1(ctrl_out[3]),
        .O(\accumulator[15]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \accumulator[15]_i_5 
       (.I0(ARG_carry__4_n_5),
        .I1(ctrl_out[2]),
        .O(\accumulator[15]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \accumulator[19]_i_2 
       (.I0(ARG_carry__6_n_6),
        .I1(ctrl_out[9]),
        .O(\accumulator[19]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \accumulator[19]_i_3 
       (.I0(ARG_carry__6_n_7),
        .I1(ctrl_out[8]),
        .O(\accumulator[19]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \accumulator[19]_i_4 
       (.I0(ARG_carry__5_n_4),
        .I1(ctrl_out[7]),
        .O(\accumulator[19]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \accumulator[19]_i_5 
       (.I0(ARG_carry__5_n_5),
        .I1(ctrl_out[6]),
        .O(\accumulator[19]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \accumulator[23]_i_2 
       (.I0(in0),
        .I1(ctrl_out[13]),
        .O(\accumulator[23]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \accumulator[23]_i_3 
       (.I0(in0),
        .I1(ctrl_out[12]),
        .O(\accumulator[23]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \accumulator[23]_i_4 
       (.I0(in0),
        .I1(ctrl_out[11]),
        .O(\accumulator[23]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \accumulator[23]_i_5 
       (.I0(ARG_carry__6_n_5),
        .I1(ctrl_out[10]),
        .O(\accumulator[23]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \accumulator[25]_i_2 
       (.I0(in0),
        .I1(accumulator_reg[27]),
        .O(\accumulator[25]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \accumulator[25]_i_3 
       (.I0(in0),
        .I1(accumulator_reg[26]),
        .O(\accumulator[25]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \accumulator[25]_i_4 
       (.I0(in0),
        .I1(ctrl_out[15]),
        .O(\accumulator[25]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \accumulator[25]_i_5 
       (.I0(in0),
        .I1(ctrl_out[14]),
        .O(\accumulator[25]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \accumulator[28]_i_2 
       (.I0(in0),
        .I1(accumulator_reg[31]),
        .O(\accumulator[28]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \accumulator[28]_i_3 
       (.I0(in0),
        .I1(accumulator_reg[30]),
        .O(\accumulator[28]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \accumulator[28]_i_4 
       (.I0(in0),
        .I1(accumulator_reg[29]),
        .O(\accumulator[28]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \accumulator[28]_i_5 
       (.I0(in0),
        .I1(accumulator_reg[28]),
        .O(\accumulator[28]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \accumulator[4]_i_2 
       (.I0(ARG_carry__3_n_6),
        .I1(accumulator_reg[7]),
        .O(\accumulator[4]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \accumulator[4]_i_3 
       (.I0(ARG_carry__3_n_7),
        .I1(accumulator_reg[6]),
        .O(\accumulator[4]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \accumulator[4]_i_4 
       (.I0(ARG_carry__2_n_4),
        .I1(accumulator_reg[5]),
        .O(\accumulator[4]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \accumulator[4]_i_5 
       (.I0(ARG_carry__2_n_5),
        .I1(accumulator_reg[4]),
        .O(\accumulator[4]_i_5_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \accumulator_reg[0] 
       (.C(clk),
        .CE(1'b1),
        .D(\accumulator_reg[0]_i_1_n_7 ),
        .Q(accumulator_reg[0]),
        .R(reset));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \accumulator_reg[0]_i_1 
       (.CI(1'b0),
        .CO({\accumulator_reg[0]_i_1_n_0 ,\accumulator_reg[0]_i_1_n_1 ,\accumulator_reg[0]_i_1_n_2 ,\accumulator_reg[0]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({ARG_carry__2_n_6,ARG_carry__2_n_7,ARG_carry__1_n_4,ARG_carry__1_n_5}),
        .O({\accumulator_reg[0]_i_1_n_4 ,\accumulator_reg[0]_i_1_n_5 ,\accumulator_reg[0]_i_1_n_6 ,\accumulator_reg[0]_i_1_n_7 }),
        .S({\accumulator[0]_i_2_n_0 ,\accumulator[0]_i_3_n_0 ,\accumulator[0]_i_4_n_0 ,\accumulator[0]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \accumulator_reg[10] 
       (.C(clk),
        .CE(1'b1),
        .D(\accumulator_reg[11]_i_1_n_5 ),
        .Q(ctrl_out[0]),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \accumulator_reg[11] 
       (.C(clk),
        .CE(1'b1),
        .D(\accumulator_reg[11]_i_1_n_4 ),
        .Q(ctrl_out[1]),
        .R(reset));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \accumulator_reg[11]_i_1 
       (.CI(\accumulator_reg[4]_i_1_n_0 ),
        .CO({\accumulator_reg[11]_i_1_n_0 ,\accumulator_reg[11]_i_1_n_1 ,\accumulator_reg[11]_i_1_n_2 ,\accumulator_reg[11]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({ARG_carry__4_n_6,ARG_carry__4_n_7,ARG_carry__3_n_4,ARG_carry__3_n_5}),
        .O({\accumulator_reg[11]_i_1_n_4 ,\accumulator_reg[11]_i_1_n_5 ,\accumulator_reg[11]_i_1_n_6 ,\accumulator_reg[11]_i_1_n_7 }),
        .S({\accumulator[11]_i_2_n_0 ,\accumulator[11]_i_3_n_0 ,\accumulator[11]_i_4_n_0 ,\accumulator[11]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \accumulator_reg[12] 
       (.C(clk),
        .CE(1'b1),
        .D(\accumulator_reg[15]_i_1_n_7 ),
        .Q(ctrl_out[2]),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \accumulator_reg[13] 
       (.C(clk),
        .CE(1'b1),
        .D(\accumulator_reg[15]_i_1_n_6 ),
        .Q(ctrl_out[3]),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \accumulator_reg[14] 
       (.C(clk),
        .CE(1'b1),
        .D(\accumulator_reg[15]_i_1_n_5 ),
        .Q(ctrl_out[4]),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \accumulator_reg[15] 
       (.C(clk),
        .CE(1'b1),
        .D(\accumulator_reg[15]_i_1_n_4 ),
        .Q(ctrl_out[5]),
        .R(reset));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \accumulator_reg[15]_i_1 
       (.CI(\accumulator_reg[11]_i_1_n_0 ),
        .CO({\accumulator_reg[15]_i_1_n_0 ,\accumulator_reg[15]_i_1_n_1 ,\accumulator_reg[15]_i_1_n_2 ,\accumulator_reg[15]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({ARG_carry__5_n_6,ARG_carry__5_n_7,ARG_carry__4_n_4,ARG_carry__4_n_5}),
        .O({\accumulator_reg[15]_i_1_n_4 ,\accumulator_reg[15]_i_1_n_5 ,\accumulator_reg[15]_i_1_n_6 ,\accumulator_reg[15]_i_1_n_7 }),
        .S({\accumulator[15]_i_2_n_0 ,\accumulator[15]_i_3_n_0 ,\accumulator[15]_i_4_n_0 ,\accumulator[15]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \accumulator_reg[16] 
       (.C(clk),
        .CE(1'b1),
        .D(\accumulator_reg[19]_i_1_n_7 ),
        .Q(ctrl_out[6]),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \accumulator_reg[17] 
       (.C(clk),
        .CE(1'b1),
        .D(\accumulator_reg[19]_i_1_n_6 ),
        .Q(ctrl_out[7]),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \accumulator_reg[18] 
       (.C(clk),
        .CE(1'b1),
        .D(\accumulator_reg[19]_i_1_n_5 ),
        .Q(ctrl_out[8]),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \accumulator_reg[19] 
       (.C(clk),
        .CE(1'b1),
        .D(\accumulator_reg[19]_i_1_n_4 ),
        .Q(ctrl_out[9]),
        .R(reset));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \accumulator_reg[19]_i_1 
       (.CI(\accumulator_reg[15]_i_1_n_0 ),
        .CO({\accumulator_reg[19]_i_1_n_0 ,\accumulator_reg[19]_i_1_n_1 ,\accumulator_reg[19]_i_1_n_2 ,\accumulator_reg[19]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({ARG_carry__6_n_6,ARG_carry__6_n_7,ARG_carry__5_n_4,ARG_carry__5_n_5}),
        .O({\accumulator_reg[19]_i_1_n_4 ,\accumulator_reg[19]_i_1_n_5 ,\accumulator_reg[19]_i_1_n_6 ,\accumulator_reg[19]_i_1_n_7 }),
        .S({\accumulator[19]_i_2_n_0 ,\accumulator[19]_i_3_n_0 ,\accumulator[19]_i_4_n_0 ,\accumulator[19]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \accumulator_reg[1] 
       (.C(clk),
        .CE(1'b1),
        .D(\accumulator_reg[0]_i_1_n_6 ),
        .Q(accumulator_reg[1]),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \accumulator_reg[20] 
       (.C(clk),
        .CE(1'b1),
        .D(\accumulator_reg[23]_i_1_n_7 ),
        .Q(ctrl_out[10]),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \accumulator_reg[21] 
       (.C(clk),
        .CE(1'b1),
        .D(\accumulator_reg[23]_i_1_n_6 ),
        .Q(ctrl_out[11]),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \accumulator_reg[22] 
       (.C(clk),
        .CE(1'b1),
        .D(\accumulator_reg[23]_i_1_n_5 ),
        .Q(ctrl_out[12]),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \accumulator_reg[23] 
       (.C(clk),
        .CE(1'b1),
        .D(\accumulator_reg[23]_i_1_n_4 ),
        .Q(ctrl_out[13]),
        .R(reset));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \accumulator_reg[23]_i_1 
       (.CI(\accumulator_reg[19]_i_1_n_0 ),
        .CO({\accumulator_reg[23]_i_1_n_0 ,\accumulator_reg[23]_i_1_n_1 ,\accumulator_reg[23]_i_1_n_2 ,\accumulator_reg[23]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({in0,in0,in0,ARG_carry__6_n_5}),
        .O({\accumulator_reg[23]_i_1_n_4 ,\accumulator_reg[23]_i_1_n_5 ,\accumulator_reg[23]_i_1_n_6 ,\accumulator_reg[23]_i_1_n_7 }),
        .S({\accumulator[23]_i_2_n_0 ,\accumulator[23]_i_3_n_0 ,\accumulator[23]_i_4_n_0 ,\accumulator[23]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \accumulator_reg[24] 
       (.C(clk),
        .CE(1'b1),
        .D(\accumulator_reg[25]_i_1_n_7 ),
        .Q(ctrl_out[14]),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \accumulator_reg[25] 
       (.C(clk),
        .CE(1'b1),
        .D(\accumulator_reg[25]_i_1_n_6 ),
        .Q(ctrl_out[15]),
        .R(reset));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \accumulator_reg[25]_i_1 
       (.CI(\accumulator_reg[23]_i_1_n_0 ),
        .CO({\accumulator_reg[25]_i_1_n_0 ,\accumulator_reg[25]_i_1_n_1 ,\accumulator_reg[25]_i_1_n_2 ,\accumulator_reg[25]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({in0,in0,in0,in0}),
        .O({\accumulator_reg[25]_i_1_n_4 ,\accumulator_reg[25]_i_1_n_5 ,\accumulator_reg[25]_i_1_n_6 ,\accumulator_reg[25]_i_1_n_7 }),
        .S({\accumulator[25]_i_2_n_0 ,\accumulator[25]_i_3_n_0 ,\accumulator[25]_i_4_n_0 ,\accumulator[25]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \accumulator_reg[26] 
       (.C(clk),
        .CE(1'b1),
        .D(\accumulator_reg[25]_i_1_n_5 ),
        .Q(accumulator_reg[26]),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \accumulator_reg[27] 
       (.C(clk),
        .CE(1'b1),
        .D(\accumulator_reg[25]_i_1_n_4 ),
        .Q(accumulator_reg[27]),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \accumulator_reg[28] 
       (.C(clk),
        .CE(1'b1),
        .D(\accumulator_reg[28]_i_1_n_7 ),
        .Q(accumulator_reg[28]),
        .R(reset));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \accumulator_reg[28]_i_1 
       (.CI(\accumulator_reg[25]_i_1_n_0 ),
        .CO({\NLW_accumulator_reg[28]_i_1_CO_UNCONNECTED [3],\accumulator_reg[28]_i_1_n_1 ,\accumulator_reg[28]_i_1_n_2 ,\accumulator_reg[28]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,in0,in0,in0}),
        .O({\accumulator_reg[28]_i_1_n_4 ,\accumulator_reg[28]_i_1_n_5 ,\accumulator_reg[28]_i_1_n_6 ,\accumulator_reg[28]_i_1_n_7 }),
        .S({\accumulator[28]_i_2_n_0 ,\accumulator[28]_i_3_n_0 ,\accumulator[28]_i_4_n_0 ,\accumulator[28]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \accumulator_reg[29] 
       (.C(clk),
        .CE(1'b1),
        .D(\accumulator_reg[28]_i_1_n_6 ),
        .Q(accumulator_reg[29]),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \accumulator_reg[2] 
       (.C(clk),
        .CE(1'b1),
        .D(\accumulator_reg[0]_i_1_n_5 ),
        .Q(accumulator_reg[2]),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \accumulator_reg[30] 
       (.C(clk),
        .CE(1'b1),
        .D(\accumulator_reg[28]_i_1_n_5 ),
        .Q(accumulator_reg[30]),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \accumulator_reg[31] 
       (.C(clk),
        .CE(1'b1),
        .D(\accumulator_reg[28]_i_1_n_4 ),
        .Q(accumulator_reg[31]),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \accumulator_reg[3] 
       (.C(clk),
        .CE(1'b1),
        .D(\accumulator_reg[0]_i_1_n_4 ),
        .Q(accumulator_reg[3]),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \accumulator_reg[4] 
       (.C(clk),
        .CE(1'b1),
        .D(\accumulator_reg[4]_i_1_n_7 ),
        .Q(accumulator_reg[4]),
        .R(reset));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \accumulator_reg[4]_i_1 
       (.CI(\accumulator_reg[0]_i_1_n_0 ),
        .CO({\accumulator_reg[4]_i_1_n_0 ,\accumulator_reg[4]_i_1_n_1 ,\accumulator_reg[4]_i_1_n_2 ,\accumulator_reg[4]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({ARG_carry__3_n_6,ARG_carry__3_n_7,ARG_carry__2_n_4,ARG_carry__2_n_5}),
        .O({\accumulator_reg[4]_i_1_n_4 ,\accumulator_reg[4]_i_1_n_5 ,\accumulator_reg[4]_i_1_n_6 ,\accumulator_reg[4]_i_1_n_7 }),
        .S({\accumulator[4]_i_2_n_0 ,\accumulator[4]_i_3_n_0 ,\accumulator[4]_i_4_n_0 ,\accumulator[4]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \accumulator_reg[5] 
       (.C(clk),
        .CE(1'b1),
        .D(\accumulator_reg[4]_i_1_n_6 ),
        .Q(accumulator_reg[5]),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \accumulator_reg[6] 
       (.C(clk),
        .CE(1'b1),
        .D(\accumulator_reg[4]_i_1_n_5 ),
        .Q(accumulator_reg[6]),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \accumulator_reg[7] 
       (.C(clk),
        .CE(1'b1),
        .D(\accumulator_reg[4]_i_1_n_4 ),
        .Q(accumulator_reg[7]),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \accumulator_reg[8] 
       (.C(clk),
        .CE(1'b1),
        .D(\accumulator_reg[11]_i_1_n_7 ),
        .Q(accumulator_reg[8]),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \accumulator_reg[9] 
       (.C(clk),
        .CE(1'b1),
        .D(\accumulator_reg[11]_i_1_n_6 ),
        .Q(accumulator_reg[9]),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    pulse_sync1_reg
       (.C(clk),
        .CE(1'b1),
        .D(pulse_in),
        .Q(pulse_sync1),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    pulse_sync2_reg
       (.C(clk),
        .CE(1'b1),
        .D(pulse_sync1),
        .Q(pulse_sync2),
        .R(reset));
endmodule
`ifndef GLBL
`define GLBL
`timescale  1 ps / 1 ps

module glbl ();

    parameter ROC_WIDTH = 100000;
    parameter TOC_WIDTH = 0;
    parameter GRES_WIDTH = 10000;
    parameter GRES_START = 10000;

//--------   STARTUP Globals --------------
    wire GSR;
    wire GTS;
    wire GWE;
    wire PRLD;
    wire GRESTORE;
    tri1 p_up_tmp;
    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;

    wire PROGB_GLBL;
    wire CCLKO_GLBL;
    wire FCSBO_GLBL;
    wire [3:0] DO_GLBL;
    wire [3:0] DI_GLBL;
   
    reg GSR_int;
    reg GTS_int;
    reg PRLD_int;
    reg GRESTORE_int;

//--------   JTAG Globals --------------
    wire JTAG_TDO_GLBL;
    wire JTAG_TCK_GLBL;
    wire JTAG_TDI_GLBL;
    wire JTAG_TMS_GLBL;
    wire JTAG_TRST_GLBL;

    reg JTAG_CAPTURE_GLBL;
    reg JTAG_RESET_GLBL;
    reg JTAG_SHIFT_GLBL;
    reg JTAG_UPDATE_GLBL;
    reg JTAG_RUNTEST_GLBL;

    reg JTAG_SEL1_GLBL = 0;
    reg JTAG_SEL2_GLBL = 0 ;
    reg JTAG_SEL3_GLBL = 0;
    reg JTAG_SEL4_GLBL = 0;

    reg JTAG_USER_TDO1_GLBL = 1'bz;
    reg JTAG_USER_TDO2_GLBL = 1'bz;
    reg JTAG_USER_TDO3_GLBL = 1'bz;
    reg JTAG_USER_TDO4_GLBL = 1'bz;

    assign (strong1, weak0) GSR = GSR_int;
    assign (strong1, weak0) GTS = GTS_int;
    assign (weak1, weak0) PRLD = PRLD_int;
    assign (strong1, weak0) GRESTORE = GRESTORE_int;

    initial begin
	GSR_int = 1'b1;
	PRLD_int = 1'b1;
	#(ROC_WIDTH)
	GSR_int = 1'b0;
	PRLD_int = 1'b0;
    end

    initial begin
	GTS_int = 1'b1;
	#(TOC_WIDTH)
	GTS_int = 1'b0;
    end

    initial begin 
	GRESTORE_int = 1'b0;
	#(GRES_START);
	GRESTORE_int = 1'b1;
	#(GRES_WIDTH);
	GRESTORE_int = 1'b0;
    end

endmodule
`endif
