// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2025.1 (win64) Build 6140274 Thu May 22 00:12:29 MDT 2025
// Date        : Sun Jan  4 04:32:21 2026
// Host        : LAPTOP-L3CRKKNJ running 64-bit major release  (build 9200)
// Command     : write_verilog -force -mode funcsim
//               c:/Vivado_Debug/PLLXplore_FNPLL/FNPLL2.gen/sources_1/bd/FNPLL/ip/FNPLL_display_3bit_7seg_di_0_0/FNPLL_display_3bit_7seg_di_0_0_sim_netlist.v
// Design      : FNPLL_display_3bit_7seg_di_0_0
// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
//               or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device      : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

(* CHECK_LICENSE_TYPE = "FNPLL_display_3bit_7seg_di_0_0,display_3bit_7seg_digit,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "module_ref" *) 
(* x_core_info = "display_3bit_7seg_digit,Vivado 2025.1" *) 
(* NotValidForBitStream *)
module FNPLL_display_3bit_7seg_di_0_0
   (number,
    seg,
    dp,
    an);
  input [2:0]number;
  output [6:0]seg;
  output dp;
  output [3:0]an;

  wire \<const0> ;
  wire \<const1> ;
  wire [2:0]number;
  wire [6:0]seg;

  assign an[3] = \<const1> ;
  assign an[2] = \<const1> ;
  assign an[1] = \<const1> ;
  assign an[0] = \<const0> ;
  assign dp = \<const1> ;
  GND GND
       (.G(\<const0> ));
  FNPLL_display_3bit_7seg_di_0_0_display_3bit_7seg_digit U0
       (.number(number),
        .seg(seg[6:1]));
  VCC VCC
       (.P(\<const1> ));
  LUT3 #(
    .INIT(8'h06)) 
    \seg[0]_INST_0 
       (.I0(number[2]),
        .I1(number[0]),
        .I2(number[1]),
        .O(seg[0]));
endmodule

(* ORIG_REF_NAME = "display_3bit_7seg_digit" *) 
module FNPLL_display_3bit_7seg_di_0_0_display_3bit_7seg_digit
   (seg,
    number);
  output [5:0]seg;
  input [2:0]number;

  wire [2:0]number;
  wire [5:0]seg;

  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT3 #(
    .INIT(8'h28)) 
    \seg[1]_INST_0 
       (.I0(number[2]),
        .I1(number[1]),
        .I2(number[0]),
        .O(seg[0]));
  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT3 #(
    .INIT(8'h02)) 
    \seg[2]_INST_0 
       (.I0(number[1]),
        .I1(number[2]),
        .I2(number[0]),
        .O(seg[1]));
  (* SOFT_HLUTNM = "soft_lutpair1" *) 
  LUT3 #(
    .INIT(8'h86)) 
    \seg[3]_INST_0 
       (.I0(number[0]),
        .I1(number[2]),
        .I2(number[1]),
        .O(seg[2]));
  (* SOFT_HLUTNM = "soft_lutpair1" *) 
  LUT3 #(
    .INIT(8'hBA)) 
    \seg[4]_INST_0 
       (.I0(number[0]),
        .I1(number[1]),
        .I2(number[2]),
        .O(seg[3]));
  (* SOFT_HLUTNM = "soft_lutpair2" *) 
  LUT3 #(
    .INIT(8'hB2)) 
    \seg[5]_INST_0 
       (.I0(number[1]),
        .I1(number[2]),
        .I2(number[0]),
        .O(seg[4]));
  (* SOFT_HLUTNM = "soft_lutpair2" *) 
  LUT3 #(
    .INIT(8'h83)) 
    \seg[6]_INST_0 
       (.I0(number[0]),
        .I1(number[1]),
        .I2(number[2]),
        .O(seg[5]));
endmodule
`ifndef GLBL
`define GLBL
`timescale  1 ps / 1 ps

module glbl ();

    parameter ROC_WIDTH = 100000;
    parameter TOC_WIDTH = 0;
    parameter GRES_WIDTH = 10000;
    parameter GRES_START = 10000;

//--------   STARTUP Globals --------------
    wire GSR;
    wire GTS;
    wire GWE;
    wire PRLD;
    wire GRESTORE;
    tri1 p_up_tmp;
    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;

    wire PROGB_GLBL;
    wire CCLKO_GLBL;
    wire FCSBO_GLBL;
    wire [3:0] DO_GLBL;
    wire [3:0] DI_GLBL;
   
    reg GSR_int;
    reg GTS_int;
    reg PRLD_int;
    reg GRESTORE_int;

//--------   JTAG Globals --------------
    wire JTAG_TDO_GLBL;
    wire JTAG_TCK_GLBL;
    wire JTAG_TDI_GLBL;
    wire JTAG_TMS_GLBL;
    wire JTAG_TRST_GLBL;

    reg JTAG_CAPTURE_GLBL;
    reg JTAG_RESET_GLBL;
    reg JTAG_SHIFT_GLBL;
    reg JTAG_UPDATE_GLBL;
    reg JTAG_RUNTEST_GLBL;

    reg JTAG_SEL1_GLBL = 0;
    reg JTAG_SEL2_GLBL = 0 ;
    reg JTAG_SEL3_GLBL = 0;
    reg JTAG_SEL4_GLBL = 0;

    reg JTAG_USER_TDO1_GLBL = 1'bz;
    reg JTAG_USER_TDO2_GLBL = 1'bz;
    reg JTAG_USER_TDO3_GLBL = 1'bz;
    reg JTAG_USER_TDO4_GLBL = 1'bz;

    assign (strong1, weak0) GSR = GSR_int;
    assign (strong1, weak0) GTS = GTS_int;
    assign (weak1, weak0) PRLD = PRLD_int;
    assign (strong1, weak0) GRESTORE = GRESTORE_int;

    initial begin
	GSR_int = 1'b1;
	PRLD_int = 1'b1;
	#(ROC_WIDTH)
	GSR_int = 1'b0;
	PRLD_int = 1'b0;
    end

    initial begin
	GTS_int = 1'b1;
	#(TOC_WIDTH)
	GTS_int = 1'b0;
    end

    initial begin 
	GRESTORE_int = 1'b0;
	#(GRES_START);
	GRESTORE_int = 1'b1;
	#(GRES_WIDTH);
	GRESTORE_int = 1'b0;
    end

endmodule
`endif
