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-- IP VLNV: xilinx.com:module_ref:led_blinker:1.0
-- IP Revision: 1

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY FNPLL_led_blinker_0_0 IS
  PORT (
    clk : IN STD_LOGIC;
    led : OUT STD_LOGIC
  );
END FNPLL_led_blinker_0_0;

ARCHITECTURE FNPLL_led_blinker_0_0_arch OF FNPLL_led_blinker_0_0 IS
  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
  ATTRIBUTE DowngradeIPIdentifiedWarnings OF FNPLL_led_blinker_0_0_arch: ARCHITECTURE IS "yes";
  COMPONENT led_blinker IS
    PORT (
      clk : IN STD_LOGIC;
      led : OUT STD_LOGIC
    );
  END COMPONENT led_blinker;
  ATTRIBUTE X_INTERFACE_INFO : STRING;
  ATTRIBUTE X_INTERFACE_MODE : STRING;
  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
  ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
  ATTRIBUTE X_INTERFACE_MODE OF clk: SIGNAL IS "slave clk";
  ATTRIBUTE X_INTERFACE_PARAMETER OF clk: SIGNAL IS "XIL_INTERFACENAME clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN FNPLL_util_ds_buf_0_0_BUFG_O, INSERT_VIP 0";
BEGIN
  U0 : led_blinker
    PORT MAP (
      clk => clk,
      led => led
    );
END FNPLL_led_blinker_0_0_arch;
