// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2025.1 (win64) Build 6140274 Thu May 22 00:12:29 MDT 2025
// Date        : Sun Jan  4 13:07:45 2026
// Host        : LAPTOP-L3CRKKNJ running 64-bit major release  (build 9200)
// Command     : write_verilog -force -mode funcsim
//               c:/Vivado_Debug/PLLXplore_FNPLL/FNPLL2.gen/sources_1/bd/FNPLL/ip/FNPLL_DS_dac_0_0/FNPLL_DS_dac_0_0_sim_netlist.v
// Design      : FNPLL_DS_dac_0_0
// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
//               or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device      : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

(* CHECK_LICENSE_TYPE = "FNPLL_DS_dac_0_0,DS_dac,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "module_ref" *) 
(* x_core_info = "DS_dac,Vivado 2025.1" *) 
(* NotValidForBitStream *)
module FNPLL_DS_dac_0_0
   (clk,
    reset,
    data_in,
    pdm_out);
  (* x_interface_info = "xilinx.com:signal:clock:1.0 clk CLK" *) (* x_interface_mode = "slave clk" *) (* x_interface_parameter = "XIL_INTERFACENAME clk, ASSOCIATED_RESET reset, FREQ_HZ 10000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, INSERT_VIP 0" *) input clk;
  (* x_interface_info = "xilinx.com:signal:reset:1.0 reset RST" *) (* x_interface_mode = "slave reset" *) (* x_interface_parameter = "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input reset;
  input [15:0]data_in;
  output pdm_out;

  wire clk;
  wire [15:0]data_in;
  wire pdm_out;
  wire reset;

  FNPLL_DS_dac_0_0_DS_dac U0
       (.clk(clk),
        .data_in(data_in),
        .pdm_out(pdm_out),
        .reset(reset));
endmodule

(* ORIG_REF_NAME = "DS_dac" *) 
module FNPLL_DS_dac_0_0_DS_dac
   (pdm_out,
    reset,
    data_in,
    clk);
  output pdm_out;
  input reset;
  input [15:0]data_in;
  input clk;

  wire acc10_carry__0_i_1_n_0;
  wire acc10_carry__0_i_2_n_0;
  wire acc10_carry__0_i_3_n_0;
  wire acc10_carry__0_i_4_n_0;
  wire acc10_carry__0_n_0;
  wire acc10_carry__0_n_1;
  wire acc10_carry__0_n_2;
  wire acc10_carry__0_n_3;
  wire acc10_carry__0_n_4;
  wire acc10_carry__0_n_5;
  wire acc10_carry__0_n_6;
  wire acc10_carry__0_n_7;
  wire acc10_carry__1_i_1_n_0;
  wire acc10_carry__1_i_2_n_0;
  wire acc10_carry__1_i_3_n_0;
  wire acc10_carry__1_i_4_n_0;
  wire acc10_carry__1_n_0;
  wire acc10_carry__1_n_1;
  wire acc10_carry__1_n_2;
  wire acc10_carry__1_n_3;
  wire acc10_carry__1_n_4;
  wire acc10_carry__1_n_5;
  wire acc10_carry__1_n_6;
  wire acc10_carry__1_n_7;
  wire acc10_carry__2_i_1_n_0;
  wire acc10_carry__2_i_2_n_0;
  wire acc10_carry__2_i_3_n_0;
  wire acc10_carry__2_i_4_n_0;
  wire acc10_carry__2_n_0;
  wire acc10_carry__2_n_1;
  wire acc10_carry__2_n_2;
  wire acc10_carry__2_n_3;
  wire acc10_carry__2_n_4;
  wire acc10_carry__2_n_5;
  wire acc10_carry__2_n_6;
  wire acc10_carry__2_n_7;
  wire acc10_carry__3_i_1_n_0;
  wire acc10_carry__3_i_2_n_0;
  wire acc10_carry__3_n_3;
  wire acc10_carry__3_n_6;
  wire acc10_carry__3_n_7;
  wire acc10_carry_i_1_n_0;
  wire acc10_carry_i_2_n_0;
  wire acc10_carry_i_3_n_0;
  wire acc10_carry_i_4_n_0;
  wire acc10_carry_n_0;
  wire acc10_carry_n_1;
  wire acc10_carry_n_2;
  wire acc10_carry_n_3;
  wire acc10_carry_n_4;
  wire acc10_carry_n_5;
  wire acc10_carry_n_6;
  wire acc10_carry_n_7;
  wire \acc1_reg_n_0_[0] ;
  wire \acc1_reg_n_0_[10] ;
  wire \acc1_reg_n_0_[11] ;
  wire \acc1_reg_n_0_[12] ;
  wire \acc1_reg_n_0_[13] ;
  wire \acc1_reg_n_0_[14] ;
  wire \acc1_reg_n_0_[15] ;
  wire \acc1_reg_n_0_[16] ;
  wire \acc1_reg_n_0_[1] ;
  wire \acc1_reg_n_0_[2] ;
  wire \acc1_reg_n_0_[3] ;
  wire \acc1_reg_n_0_[4] ;
  wire \acc1_reg_n_0_[5] ;
  wire \acc1_reg_n_0_[6] ;
  wire \acc1_reg_n_0_[7] ;
  wire \acc1_reg_n_0_[8] ;
  wire \acc1_reg_n_0_[9] ;
  wire clk;
  wire [15:0]data_in;
  wire [15:0]data_in_sync1;
  wire [15:0]data_in_sync2;
  wire p_0_in;
  wire pdm_out;
  wire quant;
  wire quant_inv_i_1_n_0;
  wire reset;
  wire [3:1]NLW_acc10_carry__3_CO_UNCONNECTED;
  wire [3:2]NLW_acc10_carry__3_O_UNCONNECTED;

  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 acc10_carry
       (.CI(1'b0),
        .CO({acc10_carry_n_0,acc10_carry_n_1,acc10_carry_n_2,acc10_carry_n_3}),
        .CYINIT(1'b0),
        .DI(data_in_sync2[3:0]),
        .O({acc10_carry_n_4,acc10_carry_n_5,acc10_carry_n_6,acc10_carry_n_7}),
        .S({acc10_carry_i_1_n_0,acc10_carry_i_2_n_0,acc10_carry_i_3_n_0,acc10_carry_i_4_n_0}));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 acc10_carry__0
       (.CI(acc10_carry_n_0),
        .CO({acc10_carry__0_n_0,acc10_carry__0_n_1,acc10_carry__0_n_2,acc10_carry__0_n_3}),
        .CYINIT(1'b0),
        .DI(data_in_sync2[7:4]),
        .O({acc10_carry__0_n_4,acc10_carry__0_n_5,acc10_carry__0_n_6,acc10_carry__0_n_7}),
        .S({acc10_carry__0_i_1_n_0,acc10_carry__0_i_2_n_0,acc10_carry__0_i_3_n_0,acc10_carry__0_i_4_n_0}));
  LUT2 #(
    .INIT(4'h6)) 
    acc10_carry__0_i_1
       (.I0(data_in_sync2[7]),
        .I1(\acc1_reg_n_0_[7] ),
        .O(acc10_carry__0_i_1_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    acc10_carry__0_i_2
       (.I0(data_in_sync2[6]),
        .I1(\acc1_reg_n_0_[6] ),
        .O(acc10_carry__0_i_2_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    acc10_carry__0_i_3
       (.I0(data_in_sync2[5]),
        .I1(\acc1_reg_n_0_[5] ),
        .O(acc10_carry__0_i_3_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    acc10_carry__0_i_4
       (.I0(data_in_sync2[4]),
        .I1(\acc1_reg_n_0_[4] ),
        .O(acc10_carry__0_i_4_n_0));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 acc10_carry__1
       (.CI(acc10_carry__0_n_0),
        .CO({acc10_carry__1_n_0,acc10_carry__1_n_1,acc10_carry__1_n_2,acc10_carry__1_n_3}),
        .CYINIT(1'b0),
        .DI(data_in_sync2[11:8]),
        .O({acc10_carry__1_n_4,acc10_carry__1_n_5,acc10_carry__1_n_6,acc10_carry__1_n_7}),
        .S({acc10_carry__1_i_1_n_0,acc10_carry__1_i_2_n_0,acc10_carry__1_i_3_n_0,acc10_carry__1_i_4_n_0}));
  LUT2 #(
    .INIT(4'h6)) 
    acc10_carry__1_i_1
       (.I0(data_in_sync2[11]),
        .I1(\acc1_reg_n_0_[11] ),
        .O(acc10_carry__1_i_1_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    acc10_carry__1_i_2
       (.I0(data_in_sync2[10]),
        .I1(\acc1_reg_n_0_[10] ),
        .O(acc10_carry__1_i_2_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    acc10_carry__1_i_3
       (.I0(data_in_sync2[9]),
        .I1(\acc1_reg_n_0_[9] ),
        .O(acc10_carry__1_i_3_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    acc10_carry__1_i_4
       (.I0(data_in_sync2[8]),
        .I1(\acc1_reg_n_0_[8] ),
        .O(acc10_carry__1_i_4_n_0));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 acc10_carry__2
       (.CI(acc10_carry__1_n_0),
        .CO({acc10_carry__2_n_0,acc10_carry__2_n_1,acc10_carry__2_n_2,acc10_carry__2_n_3}),
        .CYINIT(1'b0),
        .DI({\acc1_reg_n_0_[15] ,data_in_sync2[14:12]}),
        .O({acc10_carry__2_n_4,acc10_carry__2_n_5,acc10_carry__2_n_6,acc10_carry__2_n_7}),
        .S({acc10_carry__2_i_1_n_0,acc10_carry__2_i_2_n_0,acc10_carry__2_i_3_n_0,acc10_carry__2_i_4_n_0}));
  LUT2 #(
    .INIT(4'h9)) 
    acc10_carry__2_i_1
       (.I0(\acc1_reg_n_0_[15] ),
        .I1(data_in_sync2[15]),
        .O(acc10_carry__2_i_1_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    acc10_carry__2_i_2
       (.I0(data_in_sync2[14]),
        .I1(\acc1_reg_n_0_[14] ),
        .O(acc10_carry__2_i_2_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    acc10_carry__2_i_3
       (.I0(data_in_sync2[13]),
        .I1(\acc1_reg_n_0_[13] ),
        .O(acc10_carry__2_i_3_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    acc10_carry__2_i_4
       (.I0(data_in_sync2[12]),
        .I1(\acc1_reg_n_0_[12] ),
        .O(acc10_carry__2_i_4_n_0));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 acc10_carry__3
       (.CI(acc10_carry__2_n_0),
        .CO({NLW_acc10_carry__3_CO_UNCONNECTED[3:1],acc10_carry__3_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,p_0_in}),
        .O({NLW_acc10_carry__3_O_UNCONNECTED[3:2],acc10_carry__3_n_6,acc10_carry__3_n_7}),
        .S({1'b0,1'b0,acc10_carry__3_i_1_n_0,acc10_carry__3_i_2_n_0}));
  LUT2 #(
    .INIT(4'h9)) 
    acc10_carry__3_i_1
       (.I0(\acc1_reg_n_0_[16] ),
        .I1(p_0_in),
        .O(acc10_carry__3_i_1_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    acc10_carry__3_i_2
       (.I0(\acc1_reg_n_0_[16] ),
        .I1(p_0_in),
        .O(acc10_carry__3_i_2_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    acc10_carry_i_1
       (.I0(data_in_sync2[3]),
        .I1(\acc1_reg_n_0_[3] ),
        .O(acc10_carry_i_1_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    acc10_carry_i_2
       (.I0(data_in_sync2[2]),
        .I1(\acc1_reg_n_0_[2] ),
        .O(acc10_carry_i_2_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    acc10_carry_i_3
       (.I0(data_in_sync2[1]),
        .I1(\acc1_reg_n_0_[1] ),
        .O(acc10_carry_i_3_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    acc10_carry_i_4
       (.I0(data_in_sync2[0]),
        .I1(\acc1_reg_n_0_[0] ),
        .O(acc10_carry_i_4_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \acc1_reg[0] 
       (.C(clk),
        .CE(1'b1),
        .D(acc10_carry_n_7),
        .Q(\acc1_reg_n_0_[0] ),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \acc1_reg[10] 
       (.C(clk),
        .CE(1'b1),
        .D(acc10_carry__1_n_5),
        .Q(\acc1_reg_n_0_[10] ),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \acc1_reg[11] 
       (.C(clk),
        .CE(1'b1),
        .D(acc10_carry__1_n_4),
        .Q(\acc1_reg_n_0_[11] ),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \acc1_reg[12] 
       (.C(clk),
        .CE(1'b1),
        .D(acc10_carry__2_n_7),
        .Q(\acc1_reg_n_0_[12] ),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \acc1_reg[13] 
       (.C(clk),
        .CE(1'b1),
        .D(acc10_carry__2_n_6),
        .Q(\acc1_reg_n_0_[13] ),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \acc1_reg[14] 
       (.C(clk),
        .CE(1'b1),
        .D(acc10_carry__2_n_5),
        .Q(\acc1_reg_n_0_[14] ),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \acc1_reg[15] 
       (.C(clk),
        .CE(1'b1),
        .D(acc10_carry__2_n_4),
        .Q(\acc1_reg_n_0_[15] ),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \acc1_reg[16] 
       (.C(clk),
        .CE(1'b1),
        .D(acc10_carry__3_n_7),
        .Q(\acc1_reg_n_0_[16] ),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \acc1_reg[17] 
       (.C(clk),
        .CE(1'b1),
        .D(acc10_carry__3_n_6),
        .Q(p_0_in),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \acc1_reg[1] 
       (.C(clk),
        .CE(1'b1),
        .D(acc10_carry_n_6),
        .Q(\acc1_reg_n_0_[1] ),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \acc1_reg[2] 
       (.C(clk),
        .CE(1'b1),
        .D(acc10_carry_n_5),
        .Q(\acc1_reg_n_0_[2] ),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \acc1_reg[3] 
       (.C(clk),
        .CE(1'b1),
        .D(acc10_carry_n_4),
        .Q(\acc1_reg_n_0_[3] ),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \acc1_reg[4] 
       (.C(clk),
        .CE(1'b1),
        .D(acc10_carry__0_n_7),
        .Q(\acc1_reg_n_0_[4] ),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \acc1_reg[5] 
       (.C(clk),
        .CE(1'b1),
        .D(acc10_carry__0_n_6),
        .Q(\acc1_reg_n_0_[5] ),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \acc1_reg[6] 
       (.C(clk),
        .CE(1'b1),
        .D(acc10_carry__0_n_5),
        .Q(\acc1_reg_n_0_[6] ),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \acc1_reg[7] 
       (.C(clk),
        .CE(1'b1),
        .D(acc10_carry__0_n_4),
        .Q(\acc1_reg_n_0_[7] ),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \acc1_reg[8] 
       (.C(clk),
        .CE(1'b1),
        .D(acc10_carry__1_n_7),
        .Q(\acc1_reg_n_0_[8] ),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \acc1_reg[9] 
       (.C(clk),
        .CE(1'b1),
        .D(acc10_carry__1_n_6),
        .Q(\acc1_reg_n_0_[9] ),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \data_in_sync1_reg[0] 
       (.C(clk),
        .CE(1'b1),
        .D(data_in[0]),
        .Q(data_in_sync1[0]),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \data_in_sync1_reg[10] 
       (.C(clk),
        .CE(1'b1),
        .D(data_in[10]),
        .Q(data_in_sync1[10]),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \data_in_sync1_reg[11] 
       (.C(clk),
        .CE(1'b1),
        .D(data_in[11]),
        .Q(data_in_sync1[11]),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \data_in_sync1_reg[12] 
       (.C(clk),
        .CE(1'b1),
        .D(data_in[12]),
        .Q(data_in_sync1[12]),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \data_in_sync1_reg[13] 
       (.C(clk),
        .CE(1'b1),
        .D(data_in[13]),
        .Q(data_in_sync1[13]),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \data_in_sync1_reg[14] 
       (.C(clk),
        .CE(1'b1),
        .D(data_in[14]),
        .Q(data_in_sync1[14]),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \data_in_sync1_reg[15] 
       (.C(clk),
        .CE(1'b1),
        .D(data_in[15]),
        .Q(data_in_sync1[15]),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \data_in_sync1_reg[1] 
       (.C(clk),
        .CE(1'b1),
        .D(data_in[1]),
        .Q(data_in_sync1[1]),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \data_in_sync1_reg[2] 
       (.C(clk),
        .CE(1'b1),
        .D(data_in[2]),
        .Q(data_in_sync1[2]),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \data_in_sync1_reg[3] 
       (.C(clk),
        .CE(1'b1),
        .D(data_in[3]),
        .Q(data_in_sync1[3]),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \data_in_sync1_reg[4] 
       (.C(clk),
        .CE(1'b1),
        .D(data_in[4]),
        .Q(data_in_sync1[4]),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \data_in_sync1_reg[5] 
       (.C(clk),
        .CE(1'b1),
        .D(data_in[5]),
        .Q(data_in_sync1[5]),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \data_in_sync1_reg[6] 
       (.C(clk),
        .CE(1'b1),
        .D(data_in[6]),
        .Q(data_in_sync1[6]),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \data_in_sync1_reg[7] 
       (.C(clk),
        .CE(1'b1),
        .D(data_in[7]),
        .Q(data_in_sync1[7]),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \data_in_sync1_reg[8] 
       (.C(clk),
        .CE(1'b1),
        .D(data_in[8]),
        .Q(data_in_sync1[8]),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \data_in_sync1_reg[9] 
       (.C(clk),
        .CE(1'b1),
        .D(data_in[9]),
        .Q(data_in_sync1[9]),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \data_in_sync2_reg[0] 
       (.C(clk),
        .CE(1'b1),
        .D(data_in_sync1[0]),
        .Q(data_in_sync2[0]),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \data_in_sync2_reg[10] 
       (.C(clk),
        .CE(1'b1),
        .D(data_in_sync1[10]),
        .Q(data_in_sync2[10]),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \data_in_sync2_reg[11] 
       (.C(clk),
        .CE(1'b1),
        .D(data_in_sync1[11]),
        .Q(data_in_sync2[11]),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \data_in_sync2_reg[12] 
       (.C(clk),
        .CE(1'b1),
        .D(data_in_sync1[12]),
        .Q(data_in_sync2[12]),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \data_in_sync2_reg[13] 
       (.C(clk),
        .CE(1'b1),
        .D(data_in_sync1[13]),
        .Q(data_in_sync2[13]),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \data_in_sync2_reg[14] 
       (.C(clk),
        .CE(1'b1),
        .D(data_in_sync1[14]),
        .Q(data_in_sync2[14]),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \data_in_sync2_reg[15] 
       (.C(clk),
        .CE(1'b1),
        .D(data_in_sync1[15]),
        .Q(data_in_sync2[15]),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \data_in_sync2_reg[1] 
       (.C(clk),
        .CE(1'b1),
        .D(data_in_sync1[1]),
        .Q(data_in_sync2[1]),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \data_in_sync2_reg[2] 
       (.C(clk),
        .CE(1'b1),
        .D(data_in_sync1[2]),
        .Q(data_in_sync2[2]),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \data_in_sync2_reg[3] 
       (.C(clk),
        .CE(1'b1),
        .D(data_in_sync1[3]),
        .Q(data_in_sync2[3]),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \data_in_sync2_reg[4] 
       (.C(clk),
        .CE(1'b1),
        .D(data_in_sync1[4]),
        .Q(data_in_sync2[4]),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \data_in_sync2_reg[5] 
       (.C(clk),
        .CE(1'b1),
        .D(data_in_sync1[5]),
        .Q(data_in_sync2[5]),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \data_in_sync2_reg[6] 
       (.C(clk),
        .CE(1'b1),
        .D(data_in_sync1[6]),
        .Q(data_in_sync2[6]),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \data_in_sync2_reg[7] 
       (.C(clk),
        .CE(1'b1),
        .D(data_in_sync1[7]),
        .Q(data_in_sync2[7]),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \data_in_sync2_reg[8] 
       (.C(clk),
        .CE(1'b1),
        .D(data_in_sync1[8]),
        .Q(data_in_sync2[8]),
        .R(reset));
  FDRE #(
    .INIT(1'b0)) 
    \data_in_sync2_reg[9] 
       (.C(clk),
        .CE(1'b1),
        .D(data_in_sync1[9]),
        .Q(data_in_sync2[9]),
        .R(reset));
  FDRE pdm_out_reg
       (.C(clk),
        .CE(1'b1),
        .D(quant),
        .Q(pdm_out),
        .R(reset));
  LUT2 #(
    .INIT(4'hE)) 
    quant_inv_i_1
       (.I0(p_0_in),
        .I1(reset),
        .O(quant_inv_i_1_n_0));
  (* inverted = "yes" *) 
  FDRE #(
    .INIT(1'b1)) 
    quant_reg_inv
       (.C(clk),
        .CE(1'b1),
        .D(quant_inv_i_1_n_0),
        .Q(quant),
        .R(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale  1 ps / 1 ps

module glbl ();

    parameter ROC_WIDTH = 100000;
    parameter TOC_WIDTH = 0;
    parameter GRES_WIDTH = 10000;
    parameter GRES_START = 10000;

//--------   STARTUP Globals --------------
    wire GSR;
    wire GTS;
    wire GWE;
    wire PRLD;
    wire GRESTORE;
    tri1 p_up_tmp;
    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;

    wire PROGB_GLBL;
    wire CCLKO_GLBL;
    wire FCSBO_GLBL;
    wire [3:0] DO_GLBL;
    wire [3:0] DI_GLBL;
   
    reg GSR_int;
    reg GTS_int;
    reg PRLD_int;
    reg GRESTORE_int;

//--------   JTAG Globals --------------
    wire JTAG_TDO_GLBL;
    wire JTAG_TCK_GLBL;
    wire JTAG_TDI_GLBL;
    wire JTAG_TMS_GLBL;
    wire JTAG_TRST_GLBL;

    reg JTAG_CAPTURE_GLBL;
    reg JTAG_RESET_GLBL;
    reg JTAG_SHIFT_GLBL;
    reg JTAG_UPDATE_GLBL;
    reg JTAG_RUNTEST_GLBL;

    reg JTAG_SEL1_GLBL = 0;
    reg JTAG_SEL2_GLBL = 0 ;
    reg JTAG_SEL3_GLBL = 0;
    reg JTAG_SEL4_GLBL = 0;

    reg JTAG_USER_TDO1_GLBL = 1'bz;
    reg JTAG_USER_TDO2_GLBL = 1'bz;
    reg JTAG_USER_TDO3_GLBL = 1'bz;
    reg JTAG_USER_TDO4_GLBL = 1'bz;

    assign (strong1, weak0) GSR = GSR_int;
    assign (strong1, weak0) GTS = GTS_int;
    assign (weak1, weak0) PRLD = PRLD_int;
    assign (strong1, weak0) GRESTORE = GRESTORE_int;

    initial begin
	GSR_int = 1'b1;
	PRLD_int = 1'b1;
	#(ROC_WIDTH)
	GSR_int = 1'b0;
	PRLD_int = 1'b0;
    end

    initial begin
	GTS_int = 1'b1;
	#(TOC_WIDTH)
	GTS_int = 1'b0;
    end

    initial begin 
	GRESTORE_int = 1'b0;
	#(GRES_START);
	GRESTORE_int = 1'b1;
	#(GRES_WIDTH);
	GRESTORE_int = 1'b0;
    end

endmodule
`endif
