// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2025.1 (win64) Build 6140274 Thu May 22 00:12:29 MDT 2025
// Date        : Sat Dec 20 08:46:34 2025
// Host        : LAPTOP-L3CRKKNJ running 64-bit major release  (build 9200)
// Command     : write_verilog -force -mode funcsim
//               c:/Vivado_Debug/FNPLL7/FNPLL2.gen/sources_1/bd/FNPLL/ip/FNPLL_digital_loop_filter_0_0/FNPLL_digital_loop_filter_0_0_sim_netlist.v
// Design      : FNPLL_digital_loop_filter_0_0
// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
//               or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device      : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

(* CHECK_LICENSE_TYPE = "FNPLL_digital_loop_filter_0_0,digital_loop_filter,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "module_ref" *) 
(* x_core_info = "digital_loop_filter,Vivado 2025.1" *) 
(* NotValidForBitStream *)
module FNPLL_digital_loop_filter_0_0
   (clk,
    rst_n,
    pfd_up,
    pfd_dn,
    ctrl_out);
  (* x_interface_info = "xilinx.com:signal:clock:1.0 clk CLK" *) (* x_interface_mode = "slave clk" *) (* x_interface_parameter = "XIL_INTERFACENAME clk, FREQ_HZ 300625000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, INSERT_VIP 0" *) input clk;
  (* x_interface_info = "xilinx.com:signal:reset:1.0 rst_n RST" *) (* x_interface_mode = "slave rst_n" *) (* x_interface_parameter = "XIL_INTERFACENAME rst_n, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input rst_n;
  input pfd_up;
  input pfd_dn;
  output [15:0]ctrl_out;

  wire clk;
  wire [15:0]ctrl_out;
  wire pfd_dn;
  wire pfd_up;
  wire rst_n;

  FNPLL_digital_loop_filter_0_0_digital_loop_filter U0
       (.clk(clk),
        .ctrl_out(ctrl_out),
        .pfd_dn(pfd_dn),
        .pfd_up(pfd_up),
        .rst_n(rst_n));
endmodule

(* ORIG_REF_NAME = "digital_loop_filter" *) 
module FNPLL_digital_loop_filter_0_0_digital_loop_filter
   (ctrl_out,
    rst_n,
    clk,
    pfd_dn,
    pfd_up);
  output [15:0]ctrl_out;
  input rst_n;
  input clk;
  input pfd_dn;
  input pfd_up;

  wire clk;
  wire [15:0]ctrl_out;
  wire \integrator[0]_i_2_n_0 ;
  wire \integrator[0]_i_3_n_0 ;
  wire \integrator[0]_i_4_n_0 ;
  wire \integrator[0]_i_5_n_0 ;
  wire \integrator[12]_i_2_n_0 ;
  wire \integrator[12]_i_3_n_0 ;
  wire \integrator[12]_i_4_n_0 ;
  wire \integrator[12]_i_5_n_0 ;
  wire \integrator[16]_i_2_n_0 ;
  wire \integrator[16]_i_3_n_0 ;
  wire \integrator[16]_i_4_n_0 ;
  wire \integrator[16]_i_5_n_0 ;
  wire \integrator[20]_i_2_n_0 ;
  wire \integrator[20]_i_3_n_0 ;
  wire \integrator[20]_i_4_n_0 ;
  wire \integrator[20]_i_5_n_0 ;
  wire \integrator[24]_i_2_n_0 ;
  wire \integrator[24]_i_3_n_0 ;
  wire \integrator[24]_i_4_n_0 ;
  wire \integrator[24]_i_5_n_0 ;
  wire \integrator[28]_i_2_n_0 ;
  wire \integrator[28]_i_3_n_0 ;
  wire \integrator[28]_i_4_n_0 ;
  wire \integrator[28]_i_5_n_0 ;
  wire \integrator[4]_i_2_n_0 ;
  wire \integrator[4]_i_3_n_0 ;
  wire \integrator[4]_i_4_n_0 ;
  wire \integrator[4]_i_5_n_0 ;
  wire \integrator[8]_i_2_n_0 ;
  wire \integrator[8]_i_3_n_0 ;
  wire \integrator[8]_i_4_n_0 ;
  wire \integrator[8]_i_5_n_0 ;
  wire [31:16]integrator_reg;
  wire \integrator_reg[0]_i_1_n_0 ;
  wire \integrator_reg[0]_i_1_n_1 ;
  wire \integrator_reg[0]_i_1_n_2 ;
  wire \integrator_reg[0]_i_1_n_3 ;
  wire \integrator_reg[0]_i_1_n_4 ;
  wire \integrator_reg[0]_i_1_n_5 ;
  wire \integrator_reg[0]_i_1_n_6 ;
  wire \integrator_reg[0]_i_1_n_7 ;
  wire \integrator_reg[12]_i_1_n_0 ;
  wire \integrator_reg[12]_i_1_n_1 ;
  wire \integrator_reg[12]_i_1_n_2 ;
  wire \integrator_reg[12]_i_1_n_3 ;
  wire \integrator_reg[12]_i_1_n_4 ;
  wire \integrator_reg[12]_i_1_n_5 ;
  wire \integrator_reg[12]_i_1_n_6 ;
  wire \integrator_reg[12]_i_1_n_7 ;
  wire \integrator_reg[16]_i_1_n_0 ;
  wire \integrator_reg[16]_i_1_n_1 ;
  wire \integrator_reg[16]_i_1_n_2 ;
  wire \integrator_reg[16]_i_1_n_3 ;
  wire \integrator_reg[16]_i_1_n_4 ;
  wire \integrator_reg[16]_i_1_n_5 ;
  wire \integrator_reg[16]_i_1_n_6 ;
  wire \integrator_reg[16]_i_1_n_7 ;
  wire \integrator_reg[20]_i_1_n_0 ;
  wire \integrator_reg[20]_i_1_n_1 ;
  wire \integrator_reg[20]_i_1_n_2 ;
  wire \integrator_reg[20]_i_1_n_3 ;
  wire \integrator_reg[20]_i_1_n_4 ;
  wire \integrator_reg[20]_i_1_n_5 ;
  wire \integrator_reg[20]_i_1_n_6 ;
  wire \integrator_reg[20]_i_1_n_7 ;
  wire \integrator_reg[24]_i_1_n_0 ;
  wire \integrator_reg[24]_i_1_n_1 ;
  wire \integrator_reg[24]_i_1_n_2 ;
  wire \integrator_reg[24]_i_1_n_3 ;
  wire \integrator_reg[24]_i_1_n_4 ;
  wire \integrator_reg[24]_i_1_n_5 ;
  wire \integrator_reg[24]_i_1_n_6 ;
  wire \integrator_reg[24]_i_1_n_7 ;
  wire \integrator_reg[28]_i_1_n_1 ;
  wire \integrator_reg[28]_i_1_n_2 ;
  wire \integrator_reg[28]_i_1_n_3 ;
  wire \integrator_reg[28]_i_1_n_4 ;
  wire \integrator_reg[28]_i_1_n_5 ;
  wire \integrator_reg[28]_i_1_n_6 ;
  wire \integrator_reg[28]_i_1_n_7 ;
  wire \integrator_reg[4]_i_1_n_0 ;
  wire \integrator_reg[4]_i_1_n_1 ;
  wire \integrator_reg[4]_i_1_n_2 ;
  wire \integrator_reg[4]_i_1_n_3 ;
  wire \integrator_reg[4]_i_1_n_4 ;
  wire \integrator_reg[4]_i_1_n_5 ;
  wire \integrator_reg[4]_i_1_n_6 ;
  wire \integrator_reg[4]_i_1_n_7 ;
  wire \integrator_reg[8]_i_1_n_0 ;
  wire \integrator_reg[8]_i_1_n_1 ;
  wire \integrator_reg[8]_i_1_n_2 ;
  wire \integrator_reg[8]_i_1_n_3 ;
  wire \integrator_reg[8]_i_1_n_4 ;
  wire \integrator_reg[8]_i_1_n_5 ;
  wire \integrator_reg[8]_i_1_n_6 ;
  wire \integrator_reg[8]_i_1_n_7 ;
  wire \integrator_reg_n_0_[0] ;
  wire \integrator_reg_n_0_[10] ;
  wire \integrator_reg_n_0_[11] ;
  wire \integrator_reg_n_0_[12] ;
  wire \integrator_reg_n_0_[13] ;
  wire \integrator_reg_n_0_[14] ;
  wire \integrator_reg_n_0_[15] ;
  wire \integrator_reg_n_0_[1] ;
  wire \integrator_reg_n_0_[2] ;
  wire \integrator_reg_n_0_[3] ;
  wire \integrator_reg_n_0_[4] ;
  wire \integrator_reg_n_0_[5] ;
  wire \integrator_reg_n_0_[6] ;
  wire \integrator_reg_n_0_[7] ;
  wire \integrator_reg_n_0_[8] ;
  wire \integrator_reg_n_0_[9] ;
  wire pfd_dn;
  wire pfd_up;
  wire rst_n;
  wire [3:3]\NLW_integrator_reg[28]_i_1_CO_UNCONNECTED ;

  LUT3 #(
    .INIT(8'hB4)) 
    \integrator[0]_i_2 
       (.I0(pfd_up),
        .I1(pfd_dn),
        .I2(\integrator_reg_n_0_[3] ),
        .O(\integrator[0]_i_2_n_0 ));
  LUT3 #(
    .INIT(8'hB4)) 
    \integrator[0]_i_3 
       (.I0(pfd_up),
        .I1(pfd_dn),
        .I2(\integrator_reg_n_0_[2] ),
        .O(\integrator[0]_i_3_n_0 ));
  LUT3 #(
    .INIT(8'hB4)) 
    \integrator[0]_i_4 
       (.I0(pfd_up),
        .I1(pfd_dn),
        .I2(\integrator_reg_n_0_[1] ),
        .O(\integrator[0]_i_4_n_0 ));
  LUT3 #(
    .INIT(8'h96)) 
    \integrator[0]_i_5 
       (.I0(pfd_dn),
        .I1(pfd_up),
        .I2(\integrator_reg_n_0_[0] ),
        .O(\integrator[0]_i_5_n_0 ));
  LUT3 #(
    .INIT(8'hB4)) 
    \integrator[12]_i_2 
       (.I0(pfd_up),
        .I1(pfd_dn),
        .I2(\integrator_reg_n_0_[15] ),
        .O(\integrator[12]_i_2_n_0 ));
  LUT3 #(
    .INIT(8'hB4)) 
    \integrator[12]_i_3 
       (.I0(pfd_up),
        .I1(pfd_dn),
        .I2(\integrator_reg_n_0_[14] ),
        .O(\integrator[12]_i_3_n_0 ));
  LUT3 #(
    .INIT(8'hB4)) 
    \integrator[12]_i_4 
       (.I0(pfd_up),
        .I1(pfd_dn),
        .I2(\integrator_reg_n_0_[13] ),
        .O(\integrator[12]_i_4_n_0 ));
  LUT3 #(
    .INIT(8'hB4)) 
    \integrator[12]_i_5 
       (.I0(pfd_up),
        .I1(pfd_dn),
        .I2(\integrator_reg_n_0_[12] ),
        .O(\integrator[12]_i_5_n_0 ));
  LUT3 #(
    .INIT(8'hB4)) 
    \integrator[16]_i_2 
       (.I0(pfd_up),
        .I1(pfd_dn),
        .I2(integrator_reg[19]),
        .O(\integrator[16]_i_2_n_0 ));
  LUT3 #(
    .INIT(8'hB4)) 
    \integrator[16]_i_3 
       (.I0(pfd_up),
        .I1(pfd_dn),
        .I2(integrator_reg[18]),
        .O(\integrator[16]_i_3_n_0 ));
  LUT3 #(
    .INIT(8'hB4)) 
    \integrator[16]_i_4 
       (.I0(pfd_up),
        .I1(pfd_dn),
        .I2(integrator_reg[17]),
        .O(\integrator[16]_i_4_n_0 ));
  LUT3 #(
    .INIT(8'hB4)) 
    \integrator[16]_i_5 
       (.I0(pfd_up),
        .I1(pfd_dn),
        .I2(integrator_reg[16]),
        .O(\integrator[16]_i_5_n_0 ));
  LUT3 #(
    .INIT(8'hB4)) 
    \integrator[20]_i_2 
       (.I0(pfd_up),
        .I1(pfd_dn),
        .I2(integrator_reg[23]),
        .O(\integrator[20]_i_2_n_0 ));
  LUT3 #(
    .INIT(8'hB4)) 
    \integrator[20]_i_3 
       (.I0(pfd_up),
        .I1(pfd_dn),
        .I2(integrator_reg[22]),
        .O(\integrator[20]_i_3_n_0 ));
  LUT3 #(
    .INIT(8'hB4)) 
    \integrator[20]_i_4 
       (.I0(pfd_up),
        .I1(pfd_dn),
        .I2(integrator_reg[21]),
        .O(\integrator[20]_i_4_n_0 ));
  LUT3 #(
    .INIT(8'hB4)) 
    \integrator[20]_i_5 
       (.I0(pfd_up),
        .I1(pfd_dn),
        .I2(integrator_reg[20]),
        .O(\integrator[20]_i_5_n_0 ));
  LUT3 #(
    .INIT(8'hB4)) 
    \integrator[24]_i_2 
       (.I0(pfd_up),
        .I1(pfd_dn),
        .I2(integrator_reg[27]),
        .O(\integrator[24]_i_2_n_0 ));
  LUT3 #(
    .INIT(8'hB4)) 
    \integrator[24]_i_3 
       (.I0(pfd_up),
        .I1(pfd_dn),
        .I2(integrator_reg[26]),
        .O(\integrator[24]_i_3_n_0 ));
  LUT3 #(
    .INIT(8'hB4)) 
    \integrator[24]_i_4 
       (.I0(pfd_up),
        .I1(pfd_dn),
        .I2(integrator_reg[25]),
        .O(\integrator[24]_i_4_n_0 ));
  LUT3 #(
    .INIT(8'hB4)) 
    \integrator[24]_i_5 
       (.I0(pfd_up),
        .I1(pfd_dn),
        .I2(integrator_reg[24]),
        .O(\integrator[24]_i_5_n_0 ));
  LUT3 #(
    .INIT(8'hB4)) 
    \integrator[28]_i_2 
       (.I0(pfd_up),
        .I1(pfd_dn),
        .I2(integrator_reg[31]),
        .O(\integrator[28]_i_2_n_0 ));
  LUT3 #(
    .INIT(8'hB4)) 
    \integrator[28]_i_3 
       (.I0(pfd_up),
        .I1(pfd_dn),
        .I2(integrator_reg[30]),
        .O(\integrator[28]_i_3_n_0 ));
  LUT3 #(
    .INIT(8'hB4)) 
    \integrator[28]_i_4 
       (.I0(pfd_up),
        .I1(pfd_dn),
        .I2(integrator_reg[29]),
        .O(\integrator[28]_i_4_n_0 ));
  LUT3 #(
    .INIT(8'hB4)) 
    \integrator[28]_i_5 
       (.I0(pfd_up),
        .I1(pfd_dn),
        .I2(integrator_reg[28]),
        .O(\integrator[28]_i_5_n_0 ));
  LUT3 #(
    .INIT(8'hB4)) 
    \integrator[4]_i_2 
       (.I0(pfd_up),
        .I1(pfd_dn),
        .I2(\integrator_reg_n_0_[7] ),
        .O(\integrator[4]_i_2_n_0 ));
  LUT3 #(
    .INIT(8'hB4)) 
    \integrator[4]_i_3 
       (.I0(pfd_up),
        .I1(pfd_dn),
        .I2(\integrator_reg_n_0_[6] ),
        .O(\integrator[4]_i_3_n_0 ));
  LUT3 #(
    .INIT(8'hB4)) 
    \integrator[4]_i_4 
       (.I0(pfd_up),
        .I1(pfd_dn),
        .I2(\integrator_reg_n_0_[5] ),
        .O(\integrator[4]_i_4_n_0 ));
  LUT3 #(
    .INIT(8'hB4)) 
    \integrator[4]_i_5 
       (.I0(pfd_up),
        .I1(pfd_dn),
        .I2(\integrator_reg_n_0_[4] ),
        .O(\integrator[4]_i_5_n_0 ));
  LUT3 #(
    .INIT(8'hB4)) 
    \integrator[8]_i_2 
       (.I0(pfd_up),
        .I1(pfd_dn),
        .I2(\integrator_reg_n_0_[11] ),
        .O(\integrator[8]_i_2_n_0 ));
  LUT3 #(
    .INIT(8'hB4)) 
    \integrator[8]_i_3 
       (.I0(pfd_up),
        .I1(pfd_dn),
        .I2(\integrator_reg_n_0_[10] ),
        .O(\integrator[8]_i_3_n_0 ));
  LUT3 #(
    .INIT(8'hB4)) 
    \integrator[8]_i_4 
       (.I0(pfd_up),
        .I1(pfd_dn),
        .I2(\integrator_reg_n_0_[9] ),
        .O(\integrator[8]_i_4_n_0 ));
  LUT3 #(
    .INIT(8'hB4)) 
    \integrator[8]_i_5 
       (.I0(pfd_up),
        .I1(pfd_dn),
        .I2(\integrator_reg_n_0_[8] ),
        .O(\integrator[8]_i_5_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \integrator_reg[0] 
       (.C(clk),
        .CE(1'b1),
        .D(\integrator_reg[0]_i_1_n_7 ),
        .Q(\integrator_reg_n_0_[0] ),
        .R(rst_n));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \integrator_reg[0]_i_1 
       (.CI(1'b0),
        .CO({\integrator_reg[0]_i_1_n_0 ,\integrator_reg[0]_i_1_n_1 ,\integrator_reg[0]_i_1_n_2 ,\integrator_reg[0]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({\integrator_reg_n_0_[3] ,\integrator_reg_n_0_[2] ,\integrator_reg_n_0_[1] ,\integrator_reg_n_0_[0] }),
        .O({\integrator_reg[0]_i_1_n_4 ,\integrator_reg[0]_i_1_n_5 ,\integrator_reg[0]_i_1_n_6 ,\integrator_reg[0]_i_1_n_7 }),
        .S({\integrator[0]_i_2_n_0 ,\integrator[0]_i_3_n_0 ,\integrator[0]_i_4_n_0 ,\integrator[0]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \integrator_reg[10] 
       (.C(clk),
        .CE(1'b1),
        .D(\integrator_reg[8]_i_1_n_5 ),
        .Q(\integrator_reg_n_0_[10] ),
        .R(rst_n));
  FDRE #(
    .INIT(1'b0)) 
    \integrator_reg[11] 
       (.C(clk),
        .CE(1'b1),
        .D(\integrator_reg[8]_i_1_n_4 ),
        .Q(\integrator_reg_n_0_[11] ),
        .R(rst_n));
  FDRE #(
    .INIT(1'b0)) 
    \integrator_reg[12] 
       (.C(clk),
        .CE(1'b1),
        .D(\integrator_reg[12]_i_1_n_7 ),
        .Q(\integrator_reg_n_0_[12] ),
        .R(rst_n));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \integrator_reg[12]_i_1 
       (.CI(\integrator_reg[8]_i_1_n_0 ),
        .CO({\integrator_reg[12]_i_1_n_0 ,\integrator_reg[12]_i_1_n_1 ,\integrator_reg[12]_i_1_n_2 ,\integrator_reg[12]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({\integrator_reg_n_0_[15] ,\integrator_reg_n_0_[14] ,\integrator_reg_n_0_[13] ,\integrator_reg_n_0_[12] }),
        .O({\integrator_reg[12]_i_1_n_4 ,\integrator_reg[12]_i_1_n_5 ,\integrator_reg[12]_i_1_n_6 ,\integrator_reg[12]_i_1_n_7 }),
        .S({\integrator[12]_i_2_n_0 ,\integrator[12]_i_3_n_0 ,\integrator[12]_i_4_n_0 ,\integrator[12]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \integrator_reg[13] 
       (.C(clk),
        .CE(1'b1),
        .D(\integrator_reg[12]_i_1_n_6 ),
        .Q(\integrator_reg_n_0_[13] ),
        .R(rst_n));
  FDRE #(
    .INIT(1'b0)) 
    \integrator_reg[14] 
       (.C(clk),
        .CE(1'b1),
        .D(\integrator_reg[12]_i_1_n_5 ),
        .Q(\integrator_reg_n_0_[14] ),
        .R(rst_n));
  FDRE #(
    .INIT(1'b0)) 
    \integrator_reg[15] 
       (.C(clk),
        .CE(1'b1),
        .D(\integrator_reg[12]_i_1_n_4 ),
        .Q(\integrator_reg_n_0_[15] ),
        .R(rst_n));
  FDRE #(
    .INIT(1'b0)) 
    \integrator_reg[16] 
       (.C(clk),
        .CE(1'b1),
        .D(\integrator_reg[16]_i_1_n_7 ),
        .Q(integrator_reg[16]),
        .R(rst_n));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \integrator_reg[16]_i_1 
       (.CI(\integrator_reg[12]_i_1_n_0 ),
        .CO({\integrator_reg[16]_i_1_n_0 ,\integrator_reg[16]_i_1_n_1 ,\integrator_reg[16]_i_1_n_2 ,\integrator_reg[16]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI(integrator_reg[19:16]),
        .O({\integrator_reg[16]_i_1_n_4 ,\integrator_reg[16]_i_1_n_5 ,\integrator_reg[16]_i_1_n_6 ,\integrator_reg[16]_i_1_n_7 }),
        .S({\integrator[16]_i_2_n_0 ,\integrator[16]_i_3_n_0 ,\integrator[16]_i_4_n_0 ,\integrator[16]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \integrator_reg[17] 
       (.C(clk),
        .CE(1'b1),
        .D(\integrator_reg[16]_i_1_n_6 ),
        .Q(integrator_reg[17]),
        .R(rst_n));
  FDRE #(
    .INIT(1'b0)) 
    \integrator_reg[18] 
       (.C(clk),
        .CE(1'b1),
        .D(\integrator_reg[16]_i_1_n_5 ),
        .Q(integrator_reg[18]),
        .R(rst_n));
  FDRE #(
    .INIT(1'b0)) 
    \integrator_reg[19] 
       (.C(clk),
        .CE(1'b1),
        .D(\integrator_reg[16]_i_1_n_4 ),
        .Q(integrator_reg[19]),
        .R(rst_n));
  FDRE #(
    .INIT(1'b0)) 
    \integrator_reg[1] 
       (.C(clk),
        .CE(1'b1),
        .D(\integrator_reg[0]_i_1_n_6 ),
        .Q(\integrator_reg_n_0_[1] ),
        .R(rst_n));
  FDRE #(
    .INIT(1'b0)) 
    \integrator_reg[20] 
       (.C(clk),
        .CE(1'b1),
        .D(\integrator_reg[20]_i_1_n_7 ),
        .Q(integrator_reg[20]),
        .R(rst_n));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \integrator_reg[20]_i_1 
       (.CI(\integrator_reg[16]_i_1_n_0 ),
        .CO({\integrator_reg[20]_i_1_n_0 ,\integrator_reg[20]_i_1_n_1 ,\integrator_reg[20]_i_1_n_2 ,\integrator_reg[20]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI(integrator_reg[23:20]),
        .O({\integrator_reg[20]_i_1_n_4 ,\integrator_reg[20]_i_1_n_5 ,\integrator_reg[20]_i_1_n_6 ,\integrator_reg[20]_i_1_n_7 }),
        .S({\integrator[20]_i_2_n_0 ,\integrator[20]_i_3_n_0 ,\integrator[20]_i_4_n_0 ,\integrator[20]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \integrator_reg[21] 
       (.C(clk),
        .CE(1'b1),
        .D(\integrator_reg[20]_i_1_n_6 ),
        .Q(integrator_reg[21]),
        .R(rst_n));
  FDRE #(
    .INIT(1'b0)) 
    \integrator_reg[22] 
       (.C(clk),
        .CE(1'b1),
        .D(\integrator_reg[20]_i_1_n_5 ),
        .Q(integrator_reg[22]),
        .R(rst_n));
  FDRE #(
    .INIT(1'b0)) 
    \integrator_reg[23] 
       (.C(clk),
        .CE(1'b1),
        .D(\integrator_reg[20]_i_1_n_4 ),
        .Q(integrator_reg[23]),
        .R(rst_n));
  FDRE #(
    .INIT(1'b0)) 
    \integrator_reg[24] 
       (.C(clk),
        .CE(1'b1),
        .D(\integrator_reg[24]_i_1_n_7 ),
        .Q(integrator_reg[24]),
        .R(rst_n));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \integrator_reg[24]_i_1 
       (.CI(\integrator_reg[20]_i_1_n_0 ),
        .CO({\integrator_reg[24]_i_1_n_0 ,\integrator_reg[24]_i_1_n_1 ,\integrator_reg[24]_i_1_n_2 ,\integrator_reg[24]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI(integrator_reg[27:24]),
        .O({\integrator_reg[24]_i_1_n_4 ,\integrator_reg[24]_i_1_n_5 ,\integrator_reg[24]_i_1_n_6 ,\integrator_reg[24]_i_1_n_7 }),
        .S({\integrator[24]_i_2_n_0 ,\integrator[24]_i_3_n_0 ,\integrator[24]_i_4_n_0 ,\integrator[24]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \integrator_reg[25] 
       (.C(clk),
        .CE(1'b1),
        .D(\integrator_reg[24]_i_1_n_6 ),
        .Q(integrator_reg[25]),
        .R(rst_n));
  FDRE #(
    .INIT(1'b0)) 
    \integrator_reg[26] 
       (.C(clk),
        .CE(1'b1),
        .D(\integrator_reg[24]_i_1_n_5 ),
        .Q(integrator_reg[26]),
        .R(rst_n));
  FDRE #(
    .INIT(1'b0)) 
    \integrator_reg[27] 
       (.C(clk),
        .CE(1'b1),
        .D(\integrator_reg[24]_i_1_n_4 ),
        .Q(integrator_reg[27]),
        .R(rst_n));
  FDRE #(
    .INIT(1'b0)) 
    \integrator_reg[28] 
       (.C(clk),
        .CE(1'b1),
        .D(\integrator_reg[28]_i_1_n_7 ),
        .Q(integrator_reg[28]),
        .R(rst_n));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \integrator_reg[28]_i_1 
       (.CI(\integrator_reg[24]_i_1_n_0 ),
        .CO({\NLW_integrator_reg[28]_i_1_CO_UNCONNECTED [3],\integrator_reg[28]_i_1_n_1 ,\integrator_reg[28]_i_1_n_2 ,\integrator_reg[28]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,integrator_reg[30:28]}),
        .O({\integrator_reg[28]_i_1_n_4 ,\integrator_reg[28]_i_1_n_5 ,\integrator_reg[28]_i_1_n_6 ,\integrator_reg[28]_i_1_n_7 }),
        .S({\integrator[28]_i_2_n_0 ,\integrator[28]_i_3_n_0 ,\integrator[28]_i_4_n_0 ,\integrator[28]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \integrator_reg[29] 
       (.C(clk),
        .CE(1'b1),
        .D(\integrator_reg[28]_i_1_n_6 ),
        .Q(integrator_reg[29]),
        .R(rst_n));
  FDRE #(
    .INIT(1'b0)) 
    \integrator_reg[2] 
       (.C(clk),
        .CE(1'b1),
        .D(\integrator_reg[0]_i_1_n_5 ),
        .Q(\integrator_reg_n_0_[2] ),
        .R(rst_n));
  FDRE #(
    .INIT(1'b0)) 
    \integrator_reg[30] 
       (.C(clk),
        .CE(1'b1),
        .D(\integrator_reg[28]_i_1_n_5 ),
        .Q(integrator_reg[30]),
        .R(rst_n));
  FDRE #(
    .INIT(1'b0)) 
    \integrator_reg[31] 
       (.C(clk),
        .CE(1'b1),
        .D(\integrator_reg[28]_i_1_n_4 ),
        .Q(integrator_reg[31]),
        .R(rst_n));
  FDRE #(
    .INIT(1'b0)) 
    \integrator_reg[3] 
       (.C(clk),
        .CE(1'b1),
        .D(\integrator_reg[0]_i_1_n_4 ),
        .Q(\integrator_reg_n_0_[3] ),
        .R(rst_n));
  FDRE #(
    .INIT(1'b0)) 
    \integrator_reg[4] 
       (.C(clk),
        .CE(1'b1),
        .D(\integrator_reg[4]_i_1_n_7 ),
        .Q(\integrator_reg_n_0_[4] ),
        .R(rst_n));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \integrator_reg[4]_i_1 
       (.CI(\integrator_reg[0]_i_1_n_0 ),
        .CO({\integrator_reg[4]_i_1_n_0 ,\integrator_reg[4]_i_1_n_1 ,\integrator_reg[4]_i_1_n_2 ,\integrator_reg[4]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({\integrator_reg_n_0_[7] ,\integrator_reg_n_0_[6] ,\integrator_reg_n_0_[5] ,\integrator_reg_n_0_[4] }),
        .O({\integrator_reg[4]_i_1_n_4 ,\integrator_reg[4]_i_1_n_5 ,\integrator_reg[4]_i_1_n_6 ,\integrator_reg[4]_i_1_n_7 }),
        .S({\integrator[4]_i_2_n_0 ,\integrator[4]_i_3_n_0 ,\integrator[4]_i_4_n_0 ,\integrator[4]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \integrator_reg[5] 
       (.C(clk),
        .CE(1'b1),
        .D(\integrator_reg[4]_i_1_n_6 ),
        .Q(\integrator_reg_n_0_[5] ),
        .R(rst_n));
  FDRE #(
    .INIT(1'b0)) 
    \integrator_reg[6] 
       (.C(clk),
        .CE(1'b1),
        .D(\integrator_reg[4]_i_1_n_5 ),
        .Q(\integrator_reg_n_0_[6] ),
        .R(rst_n));
  FDRE #(
    .INIT(1'b0)) 
    \integrator_reg[7] 
       (.C(clk),
        .CE(1'b1),
        .D(\integrator_reg[4]_i_1_n_4 ),
        .Q(\integrator_reg_n_0_[7] ),
        .R(rst_n));
  FDRE #(
    .INIT(1'b0)) 
    \integrator_reg[8] 
       (.C(clk),
        .CE(1'b1),
        .D(\integrator_reg[8]_i_1_n_7 ),
        .Q(\integrator_reg_n_0_[8] ),
        .R(rst_n));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \integrator_reg[8]_i_1 
       (.CI(\integrator_reg[4]_i_1_n_0 ),
        .CO({\integrator_reg[8]_i_1_n_0 ,\integrator_reg[8]_i_1_n_1 ,\integrator_reg[8]_i_1_n_2 ,\integrator_reg[8]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({\integrator_reg_n_0_[11] ,\integrator_reg_n_0_[10] ,\integrator_reg_n_0_[9] ,\integrator_reg_n_0_[8] }),
        .O({\integrator_reg[8]_i_1_n_4 ,\integrator_reg[8]_i_1_n_5 ,\integrator_reg[8]_i_1_n_6 ,\integrator_reg[8]_i_1_n_7 }),
        .S({\integrator[8]_i_2_n_0 ,\integrator[8]_i_3_n_0 ,\integrator[8]_i_4_n_0 ,\integrator[8]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \integrator_reg[9] 
       (.C(clk),
        .CE(1'b1),
        .D(\integrator_reg[8]_i_1_n_6 ),
        .Q(\integrator_reg_n_0_[9] ),
        .R(rst_n));
  FDRE #(
    .INIT(1'b0)) 
    \output_reg_reg[0] 
       (.C(clk),
        .CE(1'b1),
        .D(integrator_reg[16]),
        .Q(ctrl_out[0]),
        .R(rst_n));
  FDRE #(
    .INIT(1'b0)) 
    \output_reg_reg[10] 
       (.C(clk),
        .CE(1'b1),
        .D(integrator_reg[26]),
        .Q(ctrl_out[10]),
        .R(rst_n));
  FDRE #(
    .INIT(1'b0)) 
    \output_reg_reg[11] 
       (.C(clk),
        .CE(1'b1),
        .D(integrator_reg[27]),
        .Q(ctrl_out[11]),
        .R(rst_n));
  FDRE #(
    .INIT(1'b0)) 
    \output_reg_reg[12] 
       (.C(clk),
        .CE(1'b1),
        .D(integrator_reg[28]),
        .Q(ctrl_out[12]),
        .R(rst_n));
  FDRE #(
    .INIT(1'b0)) 
    \output_reg_reg[13] 
       (.C(clk),
        .CE(1'b1),
        .D(integrator_reg[29]),
        .Q(ctrl_out[13]),
        .R(rst_n));
  FDRE #(
    .INIT(1'b0)) 
    \output_reg_reg[14] 
       (.C(clk),
        .CE(1'b1),
        .D(integrator_reg[30]),
        .Q(ctrl_out[14]),
        .R(rst_n));
  FDRE #(
    .INIT(1'b0)) 
    \output_reg_reg[15] 
       (.C(clk),
        .CE(1'b1),
        .D(integrator_reg[31]),
        .Q(ctrl_out[15]),
        .R(rst_n));
  FDRE #(
    .INIT(1'b0)) 
    \output_reg_reg[1] 
       (.C(clk),
        .CE(1'b1),
        .D(integrator_reg[17]),
        .Q(ctrl_out[1]),
        .R(rst_n));
  FDRE #(
    .INIT(1'b0)) 
    \output_reg_reg[2] 
       (.C(clk),
        .CE(1'b1),
        .D(integrator_reg[18]),
        .Q(ctrl_out[2]),
        .R(rst_n));
  FDRE #(
    .INIT(1'b0)) 
    \output_reg_reg[3] 
       (.C(clk),
        .CE(1'b1),
        .D(integrator_reg[19]),
        .Q(ctrl_out[3]),
        .R(rst_n));
  FDRE #(
    .INIT(1'b0)) 
    \output_reg_reg[4] 
       (.C(clk),
        .CE(1'b1),
        .D(integrator_reg[20]),
        .Q(ctrl_out[4]),
        .R(rst_n));
  FDRE #(
    .INIT(1'b0)) 
    \output_reg_reg[5] 
       (.C(clk),
        .CE(1'b1),
        .D(integrator_reg[21]),
        .Q(ctrl_out[5]),
        .R(rst_n));
  FDRE #(
    .INIT(1'b0)) 
    \output_reg_reg[6] 
       (.C(clk),
        .CE(1'b1),
        .D(integrator_reg[22]),
        .Q(ctrl_out[6]),
        .R(rst_n));
  FDRE #(
    .INIT(1'b0)) 
    \output_reg_reg[7] 
       (.C(clk),
        .CE(1'b1),
        .D(integrator_reg[23]),
        .Q(ctrl_out[7]),
        .R(rst_n));
  FDRE #(
    .INIT(1'b0)) 
    \output_reg_reg[8] 
       (.C(clk),
        .CE(1'b1),
        .D(integrator_reg[24]),
        .Q(ctrl_out[8]),
        .R(rst_n));
  FDRE #(
    .INIT(1'b0)) 
    \output_reg_reg[9] 
       (.C(clk),
        .CE(1'b1),
        .D(integrator_reg[25]),
        .Q(ctrl_out[9]),
        .R(rst_n));
endmodule
`ifndef GLBL
`define GLBL
`timescale  1 ps / 1 ps

module glbl ();

    parameter ROC_WIDTH = 100000;
    parameter TOC_WIDTH = 0;
    parameter GRES_WIDTH = 10000;
    parameter GRES_START = 10000;

//--------   STARTUP Globals --------------
    wire GSR;
    wire GTS;
    wire GWE;
    wire PRLD;
    wire GRESTORE;
    tri1 p_up_tmp;
    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;

    wire PROGB_GLBL;
    wire CCLKO_GLBL;
    wire FCSBO_GLBL;
    wire [3:0] DO_GLBL;
    wire [3:0] DI_GLBL;
   
    reg GSR_int;
    reg GTS_int;
    reg PRLD_int;
    reg GRESTORE_int;

//--------   JTAG Globals --------------
    wire JTAG_TDO_GLBL;
    wire JTAG_TCK_GLBL;
    wire JTAG_TDI_GLBL;
    wire JTAG_TMS_GLBL;
    wire JTAG_TRST_GLBL;

    reg JTAG_CAPTURE_GLBL;
    reg JTAG_RESET_GLBL;
    reg JTAG_SHIFT_GLBL;
    reg JTAG_UPDATE_GLBL;
    reg JTAG_RUNTEST_GLBL;

    reg JTAG_SEL1_GLBL = 0;
    reg JTAG_SEL2_GLBL = 0 ;
    reg JTAG_SEL3_GLBL = 0;
    reg JTAG_SEL4_GLBL = 0;

    reg JTAG_USER_TDO1_GLBL = 1'bz;
    reg JTAG_USER_TDO2_GLBL = 1'bz;
    reg JTAG_USER_TDO3_GLBL = 1'bz;
    reg JTAG_USER_TDO4_GLBL = 1'bz;

    assign (strong1, weak0) GSR = GSR_int;
    assign (strong1, weak0) GTS = GTS_int;
    assign (weak1, weak0) PRLD = PRLD_int;
    assign (strong1, weak0) GRESTORE = GRESTORE_int;

    initial begin
	GSR_int = 1'b1;
	PRLD_int = 1'b1;
	#(ROC_WIDTH)
	GSR_int = 1'b0;
	PRLD_int = 1'b0;
    end

    initial begin
	GTS_int = 1'b1;
	#(TOC_WIDTH)
	GTS_int = 1'b0;
    end

    initial begin 
	GRESTORE_int = 1'b0;
	#(GRES_START);
	GRESTORE_int = 1'b1;
	#(GRES_WIDTH);
	GRESTORE_int = 1'b0;
    end

endmodule
`endif
