library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity clk_div_100 is
    port (
        clk_in   : in  std_logic;   -- input clock
        clk_out  : out std_logic    -- output clock = clk_in / 100 (50% duty cycle)
    );
end entity clk_div_100;

architecture rtl of clk_div_100 is
    signal counter : unsigned(6 downto 0) := (others => '0');  -- 0 to 99
    signal toggle  : std_logic := '0';
begin

    process(clk_in)
    begin
        if rising_edge(clk_in) then
            if counter = 24 then
                toggle  <= not toggle;
                counter <= (others => '0');
            else
                counter <= counter + 1;
            end if;
        end if;
    end process;

    -- Output has perfect 50% duty cycle: high for 50 clocks, low for 50 clocks
    clk_out <= toggle;

end architecture rtl;