// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2025.1 (win64) Build 6140274 Thu May 22 00:12:29 MDT 2025
// Date        : Sat Dec 20 19:37:03 2025
// Host        : LAPTOP-L3CRKKNJ running 64-bit major release  (build 9200)
// Command     : write_verilog -force -mode funcsim
//               c:/Vivado_Debug/FNPLL8/FNPLL2.gen/sources_1/bd/FNPLL/ip/FNPLL_nn2_div_0_0/FNPLL_nn2_div_0_0_sim_netlist.v
// Design      : FNPLL_nn2_div_0_0
// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
//               or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device      : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

(* CHECK_LICENSE_TYPE = "FNPLL_nn2_div_0_0,nn2_div,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "module_ref" *) 
(* x_core_info = "nn2_div,Vivado 2025.1" *) 
(* NotValidForBitStream *)
module FNPLL_nn2_div_0_0
   (clk,
    select_bit,
    count_val,
    out_pulse);
  (* x_interface_info = "xilinx.com:signal:clock:1.0 clk CLK" *) (* x_interface_mode = "slave clk" *) (* x_interface_parameter = "XIL_INTERFACENAME clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0" *) input clk;
  input select_bit;
  input [7:0]count_val;
  output out_pulse;

  wire clk;
  wire [7:0]count_val;
  wire out_pulse;
  wire select_bit;

  FNPLL_nn2_div_0_0_nn2_div U0
       (.clk(clk),
        .count_val(count_val),
        .out_pulse(out_pulse),
        .select_bit(select_bit));
endmodule

(* ORIG_REF_NAME = "nn2_div" *) 
module FNPLL_nn2_div_0_0_nn2_div
   (out_pulse,
    select_bit,
    clk,
    count_val);
  output out_pulse;
  input select_bit;
  input clk;
  input [7:0]count_val;

  wire [7:0]base_n;
  wire clk;
  wire [7:0]count_val;
  wire \counter[9]_i_2_n_0 ;
  wire [9:0]counter_reg;
  wire [8:1]current_limit;
  wire \current_limit[8]_i_2_n_0 ;
  wire \current_limit_reg_n_0_[0] ;
  wire \current_limit_reg_n_0_[1] ;
  wire \current_limit_reg_n_0_[2] ;
  wire \current_limit_reg_n_0_[3] ;
  wire \current_limit_reg_n_0_[4] ;
  wire \current_limit_reg_n_0_[5] ;
  wire \current_limit_reg_n_0_[6] ;
  wire \current_limit_reg_n_0_[7] ;
  wire \current_limit_reg_n_0_[8] ;
  wire current_mode;
  wire current_mode0;
  wire current_mode0_carry_i_1_n_0;
  wire current_mode0_carry_i_2_n_0;
  wire current_mode0_carry_i_3_n_0;
  wire current_mode0_carry_i_4_n_0;
  wire current_mode0_carry_n_1;
  wire current_mode0_carry_n_2;
  wire current_mode0_carry_n_3;
  wire current_mode_i_1_n_0;
  wire next_mode;
  wire out_pulse;
  wire out_pulse0;
  wire out_pulse0_carry_i_10_n_0;
  wire out_pulse0_carry_i_1_n_0;
  wire out_pulse0_carry_i_2_n_0;
  wire out_pulse0_carry_i_3_n_0;
  wire out_pulse0_carry_i_4_n_0;
  wire out_pulse0_carry_i_5_n_0;
  wire out_pulse0_carry_i_6_n_0;
  wire out_pulse0_carry_i_7_n_0;
  wire out_pulse0_carry_i_8_n_0;
  wire out_pulse0_carry_i_9_n_0;
  wire out_pulse0_carry_n_1;
  wire out_pulse0_carry_n_2;
  wire out_pulse0_carry_n_3;
  wire [9:0]plusOp0_in;
  wire select_bit;
  wire toggle;
  wire toggle_i_1_n_0;
  wire [3:0]NLW_current_mode0_carry_O_UNCONNECTED;
  wire [3:0]NLW_out_pulse0_carry_O_UNCONNECTED;

  FDRE \base_n_reg[0] 
       (.C(clk),
        .CE(1'b1),
        .D(count_val[0]),
        .Q(base_n[0]),
        .R(1'b0));
  FDRE \base_n_reg[1] 
       (.C(clk),
        .CE(1'b1),
        .D(count_val[1]),
        .Q(base_n[1]),
        .R(1'b0));
  FDRE \base_n_reg[2] 
       (.C(clk),
        .CE(1'b1),
        .D(count_val[2]),
        .Q(base_n[2]),
        .R(1'b0));
  FDRE \base_n_reg[3] 
       (.C(clk),
        .CE(1'b1),
        .D(count_val[3]),
        .Q(base_n[3]),
        .R(1'b0));
  FDRE \base_n_reg[4] 
       (.C(clk),
        .CE(1'b1),
        .D(count_val[4]),
        .Q(base_n[4]),
        .R(1'b0));
  FDRE \base_n_reg[5] 
       (.C(clk),
        .CE(1'b1),
        .D(count_val[5]),
        .Q(base_n[5]),
        .R(1'b0));
  FDRE \base_n_reg[6] 
       (.C(clk),
        .CE(1'b1),
        .D(count_val[6]),
        .Q(base_n[6]),
        .R(1'b0));
  FDRE \base_n_reg[7] 
       (.C(clk),
        .CE(1'b1),
        .D(count_val[7]),
        .Q(base_n[7]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair9" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \counter[0]_i_1 
       (.I0(counter_reg[0]),
        .O(plusOp0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair9" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \counter[1]_i_1 
       (.I0(counter_reg[0]),
        .I1(counter_reg[1]),
        .O(plusOp0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair5" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \counter[2]_i_1 
       (.I0(counter_reg[1]),
        .I1(counter_reg[0]),
        .I2(counter_reg[2]),
        .O(plusOp0_in[2]));
  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \counter[3]_i_1 
       (.I0(counter_reg[0]),
        .I1(counter_reg[1]),
        .I2(counter_reg[2]),
        .I3(counter_reg[3]),
        .O(plusOp0_in[3]));
  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \counter[4]_i_1 
       (.I0(counter_reg[3]),
        .I1(counter_reg[2]),
        .I2(counter_reg[1]),
        .I3(counter_reg[0]),
        .I4(counter_reg[4]),
        .O(plusOp0_in[4]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \counter[5]_i_1 
       (.I0(counter_reg[0]),
        .I1(counter_reg[1]),
        .I2(counter_reg[2]),
        .I3(counter_reg[3]),
        .I4(counter_reg[4]),
        .I5(counter_reg[5]),
        .O(plusOp0_in[5]));
  (* SOFT_HLUTNM = "soft_lutpair6" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \counter[6]_i_1 
       (.I0(\counter[9]_i_2_n_0 ),
        .I1(counter_reg[6]),
        .O(plusOp0_in[6]));
  (* SOFT_HLUTNM = "soft_lutpair6" *) 
  LUT3 #(
    .INIT(8'hB4)) 
    \counter[7]_i_1 
       (.I0(\counter[9]_i_2_n_0 ),
        .I1(counter_reg[6]),
        .I2(counter_reg[7]),
        .O(plusOp0_in[7]));
  (* SOFT_HLUTNM = "soft_lutpair1" *) 
  LUT4 #(
    .INIT(16'hF708)) 
    \counter[8]_i_1 
       (.I0(counter_reg[7]),
        .I1(counter_reg[6]),
        .I2(\counter[9]_i_2_n_0 ),
        .I3(counter_reg[8]),
        .O(plusOp0_in[8]));
  (* SOFT_HLUTNM = "soft_lutpair1" *) 
  LUT5 #(
    .INIT(32'hDFFF2000)) 
    \counter[9]_i_1 
       (.I0(counter_reg[8]),
        .I1(\counter[9]_i_2_n_0 ),
        .I2(counter_reg[6]),
        .I3(counter_reg[7]),
        .I4(counter_reg[9]),
        .O(plusOp0_in[9]));
  LUT6 #(
    .INIT(64'h7FFFFFFFFFFFFFFF)) 
    \counter[9]_i_2 
       (.I0(counter_reg[0]),
        .I1(counter_reg[1]),
        .I2(counter_reg[2]),
        .I3(counter_reg[3]),
        .I4(counter_reg[4]),
        .I5(counter_reg[5]),
        .O(\counter[9]_i_2_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \counter_reg[0] 
       (.C(clk),
        .CE(1'b1),
        .D(plusOp0_in[0]),
        .Q(counter_reg[0]),
        .R(out_pulse0));
  FDRE #(
    .INIT(1'b0)) 
    \counter_reg[1] 
       (.C(clk),
        .CE(1'b1),
        .D(plusOp0_in[1]),
        .Q(counter_reg[1]),
        .R(out_pulse0));
  FDRE #(
    .INIT(1'b0)) 
    \counter_reg[2] 
       (.C(clk),
        .CE(1'b1),
        .D(plusOp0_in[2]),
        .Q(counter_reg[2]),
        .R(out_pulse0));
  FDRE #(
    .INIT(1'b0)) 
    \counter_reg[3] 
       (.C(clk),
        .CE(1'b1),
        .D(plusOp0_in[3]),
        .Q(counter_reg[3]),
        .R(out_pulse0));
  FDRE #(
    .INIT(1'b0)) 
    \counter_reg[4] 
       (.C(clk),
        .CE(1'b1),
        .D(plusOp0_in[4]),
        .Q(counter_reg[4]),
        .R(out_pulse0));
  FDRE #(
    .INIT(1'b0)) 
    \counter_reg[5] 
       (.C(clk),
        .CE(1'b1),
        .D(plusOp0_in[5]),
        .Q(counter_reg[5]),
        .R(out_pulse0));
  FDRE #(
    .INIT(1'b0)) 
    \counter_reg[6] 
       (.C(clk),
        .CE(1'b1),
        .D(plusOp0_in[6]),
        .Q(counter_reg[6]),
        .R(out_pulse0));
  FDRE #(
    .INIT(1'b0)) 
    \counter_reg[7] 
       (.C(clk),
        .CE(1'b1),
        .D(plusOp0_in[7]),
        .Q(counter_reg[7]),
        .R(out_pulse0));
  FDRE #(
    .INIT(1'b0)) 
    \counter_reg[8] 
       (.C(clk),
        .CE(1'b1),
        .D(plusOp0_in[8]),
        .Q(counter_reg[8]),
        .R(out_pulse0));
  FDRE #(
    .INIT(1'b0)) 
    \counter_reg[9] 
       (.C(clk),
        .CE(1'b1),
        .D(plusOp0_in[9]),
        .Q(counter_reg[9]),
        .R(out_pulse0));
  (* SOFT_HLUTNM = "soft_lutpair7" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \current_limit[1]_i_1 
       (.I0(current_mode),
        .I1(toggle),
        .I2(base_n[1]),
        .O(current_limit[1]));
  (* SOFT_HLUTNM = "soft_lutpair3" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \current_limit[2]_i_1 
       (.I0(toggle),
        .I1(current_mode),
        .I2(base_n[1]),
        .I3(base_n[2]),
        .O(current_limit[2]));
  (* SOFT_HLUTNM = "soft_lutpair3" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \current_limit[3]_i_1 
       (.I0(base_n[1]),
        .I1(current_mode),
        .I2(toggle),
        .I3(base_n[2]),
        .I4(base_n[3]),
        .O(current_limit[3]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \current_limit[4]_i_1 
       (.I0(base_n[2]),
        .I1(toggle),
        .I2(current_mode),
        .I3(base_n[1]),
        .I4(base_n[3]),
        .I5(base_n[4]),
        .O(current_limit[4]));
  (* SOFT_HLUTNM = "soft_lutpair8" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \current_limit[5]_i_1 
       (.I0(\current_limit[8]_i_2_n_0 ),
        .I1(base_n[5]),
        .O(current_limit[5]));
  (* SOFT_HLUTNM = "soft_lutpair8" *) 
  LUT3 #(
    .INIT(8'hB4)) 
    \current_limit[6]_i_1 
       (.I0(\current_limit[8]_i_2_n_0 ),
        .I1(base_n[5]),
        .I2(base_n[6]),
        .O(current_limit[6]));
  (* SOFT_HLUTNM = "soft_lutpair4" *) 
  LUT4 #(
    .INIT(16'hDF20)) 
    \current_limit[7]_i_1 
       (.I0(base_n[5]),
        .I1(\current_limit[8]_i_2_n_0 ),
        .I2(base_n[6]),
        .I3(base_n[7]),
        .O(current_limit[7]));
  (* SOFT_HLUTNM = "soft_lutpair4" *) 
  LUT4 #(
    .INIT(16'h0800)) 
    \current_limit[8]_i_1 
       (.I0(base_n[7]),
        .I1(base_n[5]),
        .I2(\current_limit[8]_i_2_n_0 ),
        .I3(base_n[6]),
        .O(current_limit[8]));
  LUT6 #(
    .INIT(64'h7FFFFFFFFFFFFFFF)) 
    \current_limit[8]_i_2 
       (.I0(base_n[4]),
        .I1(base_n[2]),
        .I2(toggle),
        .I3(current_mode),
        .I4(base_n[1]),
        .I5(base_n[3]),
        .O(\current_limit[8]_i_2_n_0 ));
  FDRE \current_limit_reg[0] 
       (.C(clk),
        .CE(1'b1),
        .D(base_n[0]),
        .Q(\current_limit_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \current_limit_reg[1] 
       (.C(clk),
        .CE(1'b1),
        .D(current_limit[1]),
        .Q(\current_limit_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \current_limit_reg[2] 
       (.C(clk),
        .CE(1'b1),
        .D(current_limit[2]),
        .Q(\current_limit_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \current_limit_reg[3] 
       (.C(clk),
        .CE(1'b1),
        .D(current_limit[3]),
        .Q(\current_limit_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \current_limit_reg[4] 
       (.C(clk),
        .CE(1'b1),
        .D(current_limit[4]),
        .Q(\current_limit_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \current_limit_reg[5] 
       (.C(clk),
        .CE(1'b1),
        .D(current_limit[5]),
        .Q(\current_limit_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \current_limit_reg[6] 
       (.C(clk),
        .CE(1'b1),
        .D(current_limit[6]),
        .Q(\current_limit_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \current_limit_reg[7] 
       (.C(clk),
        .CE(1'b1),
        .D(current_limit[7]),
        .Q(\current_limit_reg_n_0_[7] ),
        .R(1'b0));
  FDRE \current_limit_reg[8] 
       (.C(clk),
        .CE(1'b1),
        .D(current_limit[8]),
        .Q(\current_limit_reg_n_0_[8] ),
        .R(1'b0));
  CARRY4 current_mode0_carry
       (.CI(1'b0),
        .CO({current_mode0,current_mode0_carry_n_1,current_mode0_carry_n_2,current_mode0_carry_n_3}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_current_mode0_carry_O_UNCONNECTED[3:0]),
        .S({current_mode0_carry_i_1_n_0,current_mode0_carry_i_2_n_0,current_mode0_carry_i_3_n_0,current_mode0_carry_i_4_n_0}));
  LUT1 #(
    .INIT(2'h1)) 
    current_mode0_carry_i_1
       (.I0(counter_reg[9]),
        .O(current_mode0_carry_i_1_n_0));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    current_mode0_carry_i_2
       (.I0(counter_reg[7]),
        .I1(\current_limit_reg_n_0_[7] ),
        .I2(counter_reg[6]),
        .I3(\current_limit_reg_n_0_[6] ),
        .I4(\current_limit_reg_n_0_[8] ),
        .I5(counter_reg[8]),
        .O(current_mode0_carry_i_2_n_0));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    current_mode0_carry_i_3
       (.I0(counter_reg[4]),
        .I1(\current_limit_reg_n_0_[4] ),
        .I2(counter_reg[3]),
        .I3(\current_limit_reg_n_0_[3] ),
        .I4(\current_limit_reg_n_0_[5] ),
        .I5(counter_reg[5]),
        .O(current_mode0_carry_i_3_n_0));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    current_mode0_carry_i_4
       (.I0(counter_reg[1]),
        .I1(\current_limit_reg_n_0_[1] ),
        .I2(counter_reg[2]),
        .I3(\current_limit_reg_n_0_[2] ),
        .I4(\current_limit_reg_n_0_[0] ),
        .I5(counter_reg[0]),
        .O(current_mode0_carry_i_4_n_0));
  LUT3 #(
    .INIT(8'hB8)) 
    current_mode_i_1
       (.I0(next_mode),
        .I1(current_mode0),
        .I2(current_mode),
        .O(current_mode_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    current_mode_reg
       (.C(clk),
        .CE(1'b1),
        .D(current_mode_i_1_n_0),
        .Q(current_mode),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    next_mode_reg
       (.C(clk),
        .CE(1'b1),
        .D(select_bit),
        .Q(next_mode),
        .R(1'b0));
  CARRY4 out_pulse0_carry
       (.CI(1'b0),
        .CO({out_pulse0,out_pulse0_carry_n_1,out_pulse0_carry_n_2,out_pulse0_carry_n_3}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_out_pulse0_carry_O_UNCONNECTED[3:0]),
        .S({out_pulse0_carry_i_1_n_0,out_pulse0_carry_i_2_n_0,out_pulse0_carry_i_3_n_0,out_pulse0_carry_i_4_n_0}));
  LUT5 #(
    .INIT(32'h2000DFFF)) 
    out_pulse0_carry_i_1
       (.I0(\current_limit_reg_n_0_[8] ),
        .I1(out_pulse0_carry_i_5_n_0),
        .I2(\current_limit_reg_n_0_[6] ),
        .I3(\current_limit_reg_n_0_[7] ),
        .I4(plusOp0_in[9]),
        .O(out_pulse0_carry_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2" *) 
  LUT3 #(
    .INIT(8'h80)) 
    out_pulse0_carry_i_10
       (.I0(\current_limit_reg_n_0_[2] ),
        .I1(\current_limit_reg_n_0_[1] ),
        .I2(\current_limit_reg_n_0_[0] ),
        .O(out_pulse0_carry_i_10_n_0));
  LUT6 #(
    .INIT(64'h8888288822228222)) 
    out_pulse0_carry_i_2
       (.I0(out_pulse0_carry_i_6_n_0),
        .I1(plusOp0_in[8]),
        .I2(\current_limit_reg_n_0_[7] ),
        .I3(\current_limit_reg_n_0_[6] ),
        .I4(out_pulse0_carry_i_5_n_0),
        .I5(\current_limit_reg_n_0_[8] ),
        .O(out_pulse0_carry_i_2_n_0));
  LUT4 #(
    .INIT(16'h2882)) 
    out_pulse0_carry_i_3
       (.I0(out_pulse0_carry_i_7_n_0),
        .I1(plusOp0_in[5]),
        .I2(\current_limit_reg_n_0_[5] ),
        .I3(out_pulse0_carry_i_8_n_0),
        .O(out_pulse0_carry_i_3_n_0));
  LUT6 #(
    .INIT(64'h8040201008040201)) 
    out_pulse0_carry_i_4
       (.I0(counter_reg[1]),
        .I1(counter_reg[0]),
        .I2(counter_reg[2]),
        .I3(\current_limit_reg_n_0_[1] ),
        .I4(\current_limit_reg_n_0_[0] ),
        .I5(\current_limit_reg_n_0_[2] ),
        .O(out_pulse0_carry_i_4_n_0));
  LUT6 #(
    .INIT(64'h7FFFFFFFFFFFFFFF)) 
    out_pulse0_carry_i_5
       (.I0(\current_limit_reg_n_0_[0] ),
        .I1(\current_limit_reg_n_0_[1] ),
        .I2(\current_limit_reg_n_0_[2] ),
        .I3(\current_limit_reg_n_0_[3] ),
        .I4(\current_limit_reg_n_0_[4] ),
        .I5(\current_limit_reg_n_0_[5] ),
        .O(out_pulse0_carry_i_5_n_0));
  LUT6 #(
    .INIT(64'h9009096006909009)) 
    out_pulse0_carry_i_6
       (.I0(counter_reg[7]),
        .I1(\current_limit_reg_n_0_[7] ),
        .I2(\counter[9]_i_2_n_0 ),
        .I3(counter_reg[6]),
        .I4(out_pulse0_carry_i_5_n_0),
        .I5(\current_limit_reg_n_0_[6] ),
        .O(out_pulse0_carry_i_6_n_0));
  LUT6 #(
    .INIT(64'h8160601818060681)) 
    out_pulse0_carry_i_7
       (.I0(counter_reg[3]),
        .I1(out_pulse0_carry_i_9_n_0),
        .I2(counter_reg[4]),
        .I3(\current_limit_reg_n_0_[3] ),
        .I4(out_pulse0_carry_i_10_n_0),
        .I5(\current_limit_reg_n_0_[4] ),
        .O(out_pulse0_carry_i_7_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2" *) 
  LUT5 #(
    .INIT(32'h80000000)) 
    out_pulse0_carry_i_8
       (.I0(\current_limit_reg_n_0_[4] ),
        .I1(\current_limit_reg_n_0_[3] ),
        .I2(\current_limit_reg_n_0_[2] ),
        .I3(\current_limit_reg_n_0_[1] ),
        .I4(\current_limit_reg_n_0_[0] ),
        .O(out_pulse0_carry_i_8_n_0));
  (* SOFT_HLUTNM = "soft_lutpair5" *) 
  LUT3 #(
    .INIT(8'h80)) 
    out_pulse0_carry_i_9
       (.I0(counter_reg[2]),
        .I1(counter_reg[1]),
        .I2(counter_reg[0]),
        .O(out_pulse0_carry_i_9_n_0));
  FDRE out_pulse_reg
       (.C(clk),
        .CE(1'b1),
        .D(out_pulse0),
        .Q(out_pulse),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair7" *) 
  LUT3 #(
    .INIT(8'h78)) 
    toggle_i_1
       (.I0(current_mode),
        .I1(out_pulse0),
        .I2(toggle),
        .O(toggle_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    toggle_reg
       (.C(clk),
        .CE(1'b1),
        .D(toggle_i_1_n_0),
        .Q(toggle),
        .R(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale  1 ps / 1 ps

module glbl ();

    parameter ROC_WIDTH = 100000;
    parameter TOC_WIDTH = 0;
    parameter GRES_WIDTH = 10000;
    parameter GRES_START = 10000;

//--------   STARTUP Globals --------------
    wire GSR;
    wire GTS;
    wire GWE;
    wire PRLD;
    wire GRESTORE;
    tri1 p_up_tmp;
    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;

    wire PROGB_GLBL;
    wire CCLKO_GLBL;
    wire FCSBO_GLBL;
    wire [3:0] DO_GLBL;
    wire [3:0] DI_GLBL;
   
    reg GSR_int;
    reg GTS_int;
    reg PRLD_int;
    reg GRESTORE_int;

//--------   JTAG Globals --------------
    wire JTAG_TDO_GLBL;
    wire JTAG_TCK_GLBL;
    wire JTAG_TDI_GLBL;
    wire JTAG_TMS_GLBL;
    wire JTAG_TRST_GLBL;

    reg JTAG_CAPTURE_GLBL;
    reg JTAG_RESET_GLBL;
    reg JTAG_SHIFT_GLBL;
    reg JTAG_UPDATE_GLBL;
    reg JTAG_RUNTEST_GLBL;

    reg JTAG_SEL1_GLBL = 0;
    reg JTAG_SEL2_GLBL = 0 ;
    reg JTAG_SEL3_GLBL = 0;
    reg JTAG_SEL4_GLBL = 0;

    reg JTAG_USER_TDO1_GLBL = 1'bz;
    reg JTAG_USER_TDO2_GLBL = 1'bz;
    reg JTAG_USER_TDO3_GLBL = 1'bz;
    reg JTAG_USER_TDO4_GLBL = 1'bz;

    assign (strong1, weak0) GSR = GSR_int;
    assign (strong1, weak0) GTS = GTS_int;
    assign (weak1, weak0) PRLD = PRLD_int;
    assign (strong1, weak0) GRESTORE = GRESTORE_int;

    initial begin
	GSR_int = 1'b1;
	PRLD_int = 1'b1;
	#(ROC_WIDTH)
	GSR_int = 1'b0;
	PRLD_int = 1'b0;
    end

    initial begin
	GTS_int = 1'b1;
	#(TOC_WIDTH)
	GTS_int = 1'b0;
    end

    initial begin 
	GRESTORE_int = 1'b0;
	#(GRES_START);
	GRESTORE_int = 1'b1;
	#(GRES_WIDTH);
	GRESTORE_int = 1'b0;
    end

endmodule
`endif
