--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
--Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2025.1 (win64) Build 6140274 Thu May 22 00:12:29 MDT 2025
--Date        : Sun Jan  4 13:06:08 2026
--Host        : LAPTOP-L3CRKKNJ running 64-bit major release  (build 9200)
--Command     : generate_target FNPLL.bd
--Design      : FNPLL
--Purpose     : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity FNPLL is
  port (
    DS_OUT : out STD_LOGIC_VECTOR ( 0 to 0 );
    D_BG : out STD_LOGIC_VECTOR ( 0 to 0 );
    UART_IN : in STD_LOGIC;
    UART_OUT : out STD_LOGIC;
    VCO_INN : in STD_LOGIC;
    an : out STD_LOGIC_VECTOR ( 3 downto 0 );
    c_out : out STD_LOGIC;
    dp : out STD_LOGIC;
    led : out STD_LOGIC;
    seg : out STD_LOGIC_VECTOR ( 6 downto 0 );
    sys_clock : in STD_LOGIC
  );
  attribute CORE_GENERATION_INFO : string;
  attribute CORE_GENERATION_INFO of FNPLL : entity is "FNPLL,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=FNPLL,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=13,numReposBlks=13,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=10,numPkgbdBlks=0,bdsource=USER,da_board_cnt=4,synth_mode=Hierarchical}";
  attribute HW_HANDOFF : string;
  attribute HW_HANDOFF of FNPLL : entity is "FNPLL.hwdef";
end FNPLL;

architecture STRUCTURE of FNPLL is
  component FNPLL_pfd_sync_0_0 is
  port (
    clk : in STD_LOGIC;
    rst_n : in STD_LOGIC;
    ref_in : in STD_LOGIC;
    fb_in : in STD_LOGIC;
    up : out STD_LOGIC;
    dn : out STD_LOGIC
  );
  end component FNPLL_pfd_sync_0_0;
  component FNPLL_digital_loop_filter_0_0 is
  port (
    clk : in STD_LOGIC;
    rst_n : in STD_LOGIC;
    pfd_up : in STD_LOGIC;
    pfd_dn : in STD_LOGIC;
    ctrl_out : out STD_LOGIC_VECTOR ( 15 downto 0 )
  );
  end component FNPLL_digital_loop_filter_0_0;
  component FNPLL_display_3bit_7seg_di_0_0 is
  port (
    number : in STD_LOGIC_VECTOR ( 2 downto 0 );
    seg : out STD_LOGIC_VECTOR ( 6 downto 0 );
    dp : out STD_LOGIC;
    an : out STD_LOGIC_VECTOR ( 3 downto 0 )
  );
  end component FNPLL_display_3bit_7seg_di_0_0;
  component FNPLL_uart_rx_tx_regs_0_0 is
  port (
    clk : in STD_LOGIC;
    rst : in STD_LOGIC;
    rx : in STD_LOGIC;
    tx : out STD_LOGIC;
    reg8_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
    reg16_out : out STD_LOGIC_VECTOR ( 15 downto 0 );
    new_data : out STD_LOGIC
  );
  end component FNPLL_uart_rx_tx_regs_0_0;
  component FNPLL_clk_wiz_0_0 is
  port (
    reset : in STD_LOGIC;
    clk_in1 : in STD_LOGIC;
    clk_out1 : out STD_LOGIC;
    clk_out2 : out STD_LOGIC;
    clk_out3 : out STD_LOGIC;
    locked : out STD_LOGIC
  );
  end component FNPLL_clk_wiz_0_0;
  component FNPLL_nn2_div_0_0 is
  port (
    vcoin : in STD_LOGIC;
    select_bit : in STD_LOGIC;
    count_val : in STD_LOGIC_VECTOR ( 7 downto 0 );
    out_pulse : out STD_LOGIC
  );
  end component FNPLL_nn2_div_0_0;
  component FNPLL_clk_div_100_0_0 is
  port (
    clk_in : in STD_LOGIC;
    clk_out : out STD_LOGIC
  );
  end component FNPLL_clk_div_100_0_0;
  component FNPLL_pass_through_0_0 is
  port (
    clk : in STD_LOGIC;
    din : in STD_LOGIC;
    dout : out STD_LOGIC
  );
  end component FNPLL_pass_through_0_0;
  component FNPLL_led_blinker_0_0 is
  port (
    clk : in STD_LOGIC;
    led : out STD_LOGIC
  );
  end component FNPLL_led_blinker_0_0;
  component FNPLL_DS_dac_0_0 is
  port (
    clk : in STD_LOGIC;
    reset : in STD_LOGIC;
    data_in : in STD_LOGIC_VECTOR ( 15 downto 0 );
    pdm_out : out STD_LOGIC
  );
  end component FNPLL_DS_dac_0_0;
  component FNPLL_DS_dac3_0_0 is
  port (
    clk : in STD_LOGIC;
    reset : in STD_LOGIC;
    data_in : in STD_LOGIC_VECTOR ( 15 downto 0 );
    pdm_out : out STD_LOGIC
  );
  end component FNPLL_DS_dac3_0_0;
  signal \^ds_out\ : STD_LOGIC;
  signal DS_dac3_0_pdm_out : STD_LOGIC;
  signal Net : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^c_out\ : STD_LOGIC;
  signal clk_div_100_0_clk_out : STD_LOGIC;
  signal clk_wiz_0_clk_out1 : STD_LOGIC;
  signal clk_wiz_0_clk_out2 : STD_LOGIC;
  signal clk_wiz_0_clk_out3 : STD_LOGIC;
  signal digital_loop_filter_0_ctrl_out : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal ilconstant_1_dout : STD_LOGIC_VECTOR ( 0 to 0 );
  signal nn2_div_0_out_pulse : STD_LOGIC;
  signal pass_through_0_dout : STD_LOGIC;
  signal pfd_sync_0_dn : STD_LOGIC;
  signal pfd_sync_0_up : STD_LOGIC;
  signal uart_rx_tx_regs_0_reg16_out : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal uart_rx_tx_regs_0_reg3_out : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_clk_wiz_0_locked_UNCONNECTED : STD_LOGIC;
  signal NLW_uart_rx_tx_regs_0_new_data_UNCONNECTED : STD_LOGIC;
  attribute X_INTERFACE_INFO : string;
  attribute X_INTERFACE_INFO of VCO_INN : signal is "xilinx.com:signal:data:1.0 DATA.VCO_INN DATA";
  attribute X_INTERFACE_PARAMETER : string;
  attribute X_INTERFACE_PARAMETER of VCO_INN : signal is "XIL_INTERFACENAME DATA.VCO_INN, LAYERED_METADATA undef";
  attribute X_INTERFACE_INFO of c_out : signal is "xilinx.com:signal:data:1.0 DATA.C_OUT DATA";
  attribute X_INTERFACE_PARAMETER of c_out : signal is "XIL_INTERFACENAME DATA.C_OUT, LAYERED_METADATA undef";
  attribute X_INTERFACE_INFO of sys_clock : signal is "xilinx.com:signal:clock:1.0 CLK.SYS_CLOCK CLK";
  attribute X_INTERFACE_PARAMETER of sys_clock : signal is "XIL_INTERFACENAME CLK.SYS_CLOCK, CLK_DOMAIN FNPLL_sys_clock, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.0";
  attribute X_INTERFACE_INFO of DS_OUT : signal is "xilinx.com:signal:data:1.0 DATA.DS_OUT DATA";
  attribute X_INTERFACE_PARAMETER of DS_OUT : signal is "XIL_INTERFACENAME DATA.DS_OUT, LAYERED_METADATA undef";
begin
  DS_OUT(0) <= \^ds_out\;
  \^c_out\ <= VCO_INN;
  c_out <= \^c_out\;
DS_dac3_0: component FNPLL_DS_dac3_0_0
     port map (
      clk => clk_div_100_0_clk_out,
      data_in(15 downto 0) => uart_rx_tx_regs_0_reg16_out(15 downto 0),
      pdm_out => DS_dac3_0_pdm_out,
      reset => ilconstant_1_dout(0)
    );
DS_dac_0: component FNPLL_DS_dac_0_0
     port map (
      clk => clk_wiz_0_clk_out3,
      data_in(15 downto 0) => digital_loop_filter_0_ctrl_out(15 downto 0),
      pdm_out => \^ds_out\,
      reset => ilconstant_1_dout(0)
    );
clk_div_100_0: component FNPLL_clk_div_100_0_0
     port map (
      clk_in => clk_wiz_0_clk_out1,
      clk_out => clk_div_100_0_clk_out
    );
clk_wiz_0: component FNPLL_clk_wiz_0_0
     port map (
      clk_in1 => sys_clock,
      clk_out1 => clk_wiz_0_clk_out1,
      clk_out2 => clk_wiz_0_clk_out2,
      clk_out3 => clk_wiz_0_clk_out3,
      locked => NLW_clk_wiz_0_locked_UNCONNECTED,
      reset => Net(0)
    );
digital_loop_filter_0: component FNPLL_digital_loop_filter_0_0
     port map (
      clk => clk_wiz_0_clk_out2,
      ctrl_out(15 downto 0) => digital_loop_filter_0_ctrl_out(15 downto 0),
      pfd_dn => pfd_sync_0_dn,
      pfd_up => pfd_sync_0_up,
      rst_n => ilconstant_1_dout(0)
    );
display_3bit_7seg_di_0: component FNPLL_display_3bit_7seg_di_0_0
     port map (
      an(3 downto 0) => an(3 downto 0),
      dp => dp,
      number(2 downto 0) => uart_rx_tx_regs_0_reg3_out(2 downto 0),
      seg(6 downto 0) => seg(6 downto 0)
    );
  Net <= B"0";
  ilconstant_1_dout <= B"0";
led_blinker_0: component FNPLL_led_blinker_0_0
     port map (
      clk => pass_through_0_dout,
      led => led
    );
nn2_div_0: component FNPLL_nn2_div_0_0
     port map (
      count_val(7 downto 0) => uart_rx_tx_regs_0_reg3_out(7 downto 0),
      out_pulse => nn2_div_0_out_pulse,
      select_bit => DS_dac3_0_pdm_out,
      vcoin => pass_through_0_dout
    );
pass_through_0: component FNPLL_pass_through_0_0
     port map (
      clk => clk_wiz_0_clk_out2,
      din => \^c_out\,
      dout => pass_through_0_dout
    );
pfd_sync_0: component FNPLL_pfd_sync_0_0
     port map (
      clk => clk_wiz_0_clk_out2,
      dn => pfd_sync_0_dn,
      fb_in => nn2_div_0_out_pulse,
      ref_in => clk_div_100_0_clk_out,
      rst_n => ilconstant_1_dout(0),
      up => pfd_sync_0_up
    );
uart_rx_tx_regs_0: component FNPLL_uart_rx_tx_regs_0_0
     port map (
      clk => clk_wiz_0_clk_out1,
      new_data => NLW_uart_rx_tx_regs_0_new_data_UNCONNECTED,
      reg16_out(15 downto 0) => uart_rx_tx_regs_0_reg16_out(15 downto 0),
      reg8_out(7 downto 0) => uart_rx_tx_regs_0_reg3_out(7 downto 0),
      rst => Net(0),
      rx => UART_IN,
      tx => UART_OUT
    );
end STRUCTURE;
