-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2025.1 (win64) Build 6140274 Thu May 22 00:12:29 MDT 2025
-- Date        : Sun Jan  4 04:32:21 2026
-- Host        : LAPTOP-L3CRKKNJ running 64-bit major release  (build 9200)
-- Command     : write_vhdl -force -mode funcsim
--               c:/Vivado_Debug/PLLXplore_FNPLL/FNPLL2.gen/sources_1/bd/FNPLL/ip/FNPLL_pfd_sync_0_0/FNPLL_pfd_sync_0_0_sim_netlist.vhdl
-- Design      : FNPLL_pfd_sync_0_0
-- Purpose     : This VHDL netlist is a functional simulation representation of the design and should not be modified or
--               synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device      : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity FNPLL_pfd_sync_0_0_pfd_sync is
  port (
    up : out STD_LOGIC;
    dn : out STD_LOGIC;
    rst_n : in STD_LOGIC;
    clk : in STD_LOGIC;
    fb_in : in STD_LOGIC;
    ref_in : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of FNPLL_pfd_sync_0_0_pfd_sync : entity is "pfd_sync";
end FNPLL_pfd_sync_0_0_pfd_sync;

architecture STRUCTURE of FNPLL_pfd_sync_0_0_pfd_sync is
  signal \^dn\ : STD_LOGIC;
  signal dn_q_i_1_n_0 : STD_LOGIC;
  signal \fb_sync_reg_n_0_[1]\ : STD_LOGIC;
  signal p_0_in : STD_LOGIC_VECTOR ( 1 to 1 );
  signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 1 to 1 );
  signal \ref_sync_reg_n_0_[1]\ : STD_LOGIC;
  signal \^up\ : STD_LOGIC;
  signal up_q_i_1_n_0 : STD_LOGIC;
begin
  dn <= \^dn\;
  up <= \^up\;
dn_q_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000F22"
    )
        port map (
      I0 => \fb_sync_reg_n_0_[1]\,
      I1 => p_0_in(1),
      I2 => \^up\,
      I3 => \^dn\,
      I4 => rst_n,
      O => dn_q_i_1_n_0
    );
dn_q_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => dn_q_i_1_n_0,
      Q => \^dn\,
      R => '0'
    );
\fb_sync_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => fb_in,
      Q => p_0_in(1),
      R => rst_n
    );
\fb_sync_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => p_0_in(1),
      Q => \fb_sync_reg_n_0_[1]\,
      R => rst_n
    );
\ref_sync_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => ref_in,
      Q => \p_0_in__0\(1),
      R => rst_n
    );
\ref_sync_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \p_0_in__0\(1),
      Q => \ref_sync_reg_n_0_[1]\,
      R => rst_n
    );
up_q_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000002F2"
    )
        port map (
      I0 => \ref_sync_reg_n_0_[1]\,
      I1 => \p_0_in__0\(1),
      I2 => \^up\,
      I3 => \^dn\,
      I4 => rst_n,
      O => up_q_i_1_n_0
    );
up_q_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => up_q_i_1_n_0,
      Q => \^up\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity FNPLL_pfd_sync_0_0 is
  port (
    clk : in STD_LOGIC;
    rst_n : in STD_LOGIC;
    ref_in : in STD_LOGIC;
    fb_in : in STD_LOGIC;
    up : out STD_LOGIC;
    dn : out STD_LOGIC
  );
  attribute NotValidForBitStream : boolean;
  attribute NotValidForBitStream of FNPLL_pfd_sync_0_0 : entity is true;
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of FNPLL_pfd_sync_0_0 : entity is "FNPLL_pfd_sync_0_0,pfd_sync,{}";
  attribute downgradeipidentifiedwarnings : string;
  attribute downgradeipidentifiedwarnings of FNPLL_pfd_sync_0_0 : entity is "yes";
  attribute ip_definition_source : string;
  attribute ip_definition_source of FNPLL_pfd_sync_0_0 : entity is "module_ref";
  attribute x_core_info : string;
  attribute x_core_info of FNPLL_pfd_sync_0_0 : entity is "pfd_sync,Vivado 2025.1";
end FNPLL_pfd_sync_0_0;

architecture STRUCTURE of FNPLL_pfd_sync_0_0 is
  attribute x_interface_info : string;
  attribute x_interface_info of clk : signal is "xilinx.com:signal:clock:1.0 clk CLK";
  attribute x_interface_mode : string;
  attribute x_interface_mode of clk : signal is "slave clk";
  attribute x_interface_parameter : string;
  attribute x_interface_parameter of clk : signal is "XIL_INTERFACENAME clk, FREQ_HZ 200416666, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, INSERT_VIP 0";
  attribute x_interface_info of rst_n : signal is "xilinx.com:signal:reset:1.0 rst_n RST";
  attribute x_interface_mode of rst_n : signal is "slave rst_n";
  attribute x_interface_parameter of rst_n : signal is "XIL_INTERFACENAME rst_n, POLARITY ACTIVE_LOW, INSERT_VIP 0";
begin
U0: entity work.FNPLL_pfd_sync_0_0_pfd_sync
     port map (
      clk => clk,
      dn => dn,
      fb_in => fb_in,
      ref_in => ref_in,
      rst_n => rst_n,
      up => up
    );
end STRUCTURE;
