-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2025.1 (win64) Build 6140274 Thu May 22 00:12:29 MDT 2025
-- Date        : Sun Jan  4 04:32:21 2026
-- Host        : LAPTOP-L3CRKKNJ running 64-bit major release  (build 9200)
-- Command     : write_vhdl -force -mode funcsim
--               c:/Vivado_Debug/PLLXplore_FNPLL/FNPLL2.gen/sources_1/bd/FNPLL/ip/FNPLL_display_3bit_7seg_di_0_0/FNPLL_display_3bit_7seg_di_0_0_sim_netlist.vhdl
-- Design      : FNPLL_display_3bit_7seg_di_0_0
-- Purpose     : This VHDL netlist is a functional simulation representation of the design and should not be modified or
--               synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device      : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity FNPLL_display_3bit_7seg_di_0_0_display_3bit_7seg_digit is
  port (
    seg : out STD_LOGIC_VECTOR ( 5 downto 0 );
    number : in STD_LOGIC_VECTOR ( 2 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of FNPLL_display_3bit_7seg_di_0_0_display_3bit_7seg_digit : entity is "display_3bit_7seg_digit";
end FNPLL_display_3bit_7seg_di_0_0_display_3bit_7seg_digit;

architecture STRUCTURE of FNPLL_display_3bit_7seg_di_0_0_display_3bit_7seg_digit is
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \seg[1]_INST_0\ : label is "soft_lutpair0";
  attribute SOFT_HLUTNM of \seg[2]_INST_0\ : label is "soft_lutpair0";
  attribute SOFT_HLUTNM of \seg[3]_INST_0\ : label is "soft_lutpair1";
  attribute SOFT_HLUTNM of \seg[4]_INST_0\ : label is "soft_lutpair1";
  attribute SOFT_HLUTNM of \seg[5]_INST_0\ : label is "soft_lutpair2";
  attribute SOFT_HLUTNM of \seg[6]_INST_0\ : label is "soft_lutpair2";
begin
\seg[1]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"28"
    )
        port map (
      I0 => number(2),
      I1 => number(1),
      I2 => number(0),
      O => seg(0)
    );
\seg[2]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"02"
    )
        port map (
      I0 => number(1),
      I1 => number(2),
      I2 => number(0),
      O => seg(1)
    );
\seg[3]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"86"
    )
        port map (
      I0 => number(0),
      I1 => number(2),
      I2 => number(1),
      O => seg(2)
    );
\seg[4]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BA"
    )
        port map (
      I0 => number(0),
      I1 => number(1),
      I2 => number(2),
      O => seg(3)
    );
\seg[5]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B2"
    )
        port map (
      I0 => number(1),
      I1 => number(2),
      I2 => number(0),
      O => seg(4)
    );
\seg[6]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"83"
    )
        port map (
      I0 => number(0),
      I1 => number(1),
      I2 => number(2),
      O => seg(5)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity FNPLL_display_3bit_7seg_di_0_0 is
  port (
    number : in STD_LOGIC_VECTOR ( 2 downto 0 );
    seg : out STD_LOGIC_VECTOR ( 6 downto 0 );
    dp : out STD_LOGIC;
    an : out STD_LOGIC_VECTOR ( 3 downto 0 )
  );
  attribute NotValidForBitStream : boolean;
  attribute NotValidForBitStream of FNPLL_display_3bit_7seg_di_0_0 : entity is true;
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of FNPLL_display_3bit_7seg_di_0_0 : entity is "FNPLL_display_3bit_7seg_di_0_0,display_3bit_7seg_digit,{}";
  attribute downgradeipidentifiedwarnings : string;
  attribute downgradeipidentifiedwarnings of FNPLL_display_3bit_7seg_di_0_0 : entity is "yes";
  attribute ip_definition_source : string;
  attribute ip_definition_source of FNPLL_display_3bit_7seg_di_0_0 : entity is "module_ref";
  attribute x_core_info : string;
  attribute x_core_info of FNPLL_display_3bit_7seg_di_0_0 : entity is "display_3bit_7seg_digit,Vivado 2025.1";
end FNPLL_display_3bit_7seg_di_0_0;

architecture STRUCTURE of FNPLL_display_3bit_7seg_di_0_0 is
  signal \<const0>\ : STD_LOGIC;
  signal \<const1>\ : STD_LOGIC;
begin
  an(3) <= \<const1>\;
  an(2) <= \<const1>\;
  an(1) <= \<const1>\;
  an(0) <= \<const0>\;
  dp <= \<const1>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
U0: entity work.FNPLL_display_3bit_7seg_di_0_0_display_3bit_7seg_digit
     port map (
      number(2 downto 0) => number(2 downto 0),
      seg(5 downto 0) => seg(6 downto 1)
    );
VCC: unisim.vcomponents.VCC
     port map (
      P => \<const1>\
    );
\seg[0]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"06"
    )
        port map (
      I0 => number(2),
      I1 => number(0),
      I2 => number(1),
      O => seg(0)
    );
end STRUCTURE;
