-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2025.1 (win64) Build 6140274 Thu May 22 00:12:29 MDT 2025
-- Date        : Sun Jan  4 13:07:45 2026
-- Host        : LAPTOP-L3CRKKNJ running 64-bit major release  (build 9200)
-- Command     : write_vhdl -force -mode funcsim
--               c:/Vivado_Debug/PLLXplore_FNPLL/FNPLL2.gen/sources_1/bd/FNPLL/ip/FNPLL_DS_dac_0_0/FNPLL_DS_dac_0_0_sim_netlist.vhdl
-- Design      : FNPLL_DS_dac_0_0
-- Purpose     : This VHDL netlist is a functional simulation representation of the design and should not be modified or
--               synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device      : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity FNPLL_DS_dac_0_0_DS_dac is
  port (
    pdm_out : out STD_LOGIC;
    reset : in STD_LOGIC;
    data_in : in STD_LOGIC_VECTOR ( 15 downto 0 );
    clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of FNPLL_DS_dac_0_0_DS_dac : entity is "DS_dac";
end FNPLL_DS_dac_0_0_DS_dac;

architecture STRUCTURE of FNPLL_DS_dac_0_0_DS_dac is
  signal \acc10_carry__0_i_1_n_0\ : STD_LOGIC;
  signal \acc10_carry__0_i_2_n_0\ : STD_LOGIC;
  signal \acc10_carry__0_i_3_n_0\ : STD_LOGIC;
  signal \acc10_carry__0_i_4_n_0\ : STD_LOGIC;
  signal \acc10_carry__0_n_0\ : STD_LOGIC;
  signal \acc10_carry__0_n_1\ : STD_LOGIC;
  signal \acc10_carry__0_n_2\ : STD_LOGIC;
  signal \acc10_carry__0_n_3\ : STD_LOGIC;
  signal \acc10_carry__0_n_4\ : STD_LOGIC;
  signal \acc10_carry__0_n_5\ : STD_LOGIC;
  signal \acc10_carry__0_n_6\ : STD_LOGIC;
  signal \acc10_carry__0_n_7\ : STD_LOGIC;
  signal \acc10_carry__1_i_1_n_0\ : STD_LOGIC;
  signal \acc10_carry__1_i_2_n_0\ : STD_LOGIC;
  signal \acc10_carry__1_i_3_n_0\ : STD_LOGIC;
  signal \acc10_carry__1_i_4_n_0\ : STD_LOGIC;
  signal \acc10_carry__1_n_0\ : STD_LOGIC;
  signal \acc10_carry__1_n_1\ : STD_LOGIC;
  signal \acc10_carry__1_n_2\ : STD_LOGIC;
  signal \acc10_carry__1_n_3\ : STD_LOGIC;
  signal \acc10_carry__1_n_4\ : STD_LOGIC;
  signal \acc10_carry__1_n_5\ : STD_LOGIC;
  signal \acc10_carry__1_n_6\ : STD_LOGIC;
  signal \acc10_carry__1_n_7\ : STD_LOGIC;
  signal \acc10_carry__2_i_1_n_0\ : STD_LOGIC;
  signal \acc10_carry__2_i_2_n_0\ : STD_LOGIC;
  signal \acc10_carry__2_i_3_n_0\ : STD_LOGIC;
  signal \acc10_carry__2_i_4_n_0\ : STD_LOGIC;
  signal \acc10_carry__2_n_0\ : STD_LOGIC;
  signal \acc10_carry__2_n_1\ : STD_LOGIC;
  signal \acc10_carry__2_n_2\ : STD_LOGIC;
  signal \acc10_carry__2_n_3\ : STD_LOGIC;
  signal \acc10_carry__2_n_4\ : STD_LOGIC;
  signal \acc10_carry__2_n_5\ : STD_LOGIC;
  signal \acc10_carry__2_n_6\ : STD_LOGIC;
  signal \acc10_carry__2_n_7\ : STD_LOGIC;
  signal \acc10_carry__3_i_1_n_0\ : STD_LOGIC;
  signal \acc10_carry__3_i_2_n_0\ : STD_LOGIC;
  signal \acc10_carry__3_n_3\ : STD_LOGIC;
  signal \acc10_carry__3_n_6\ : STD_LOGIC;
  signal \acc10_carry__3_n_7\ : STD_LOGIC;
  signal acc10_carry_i_1_n_0 : STD_LOGIC;
  signal acc10_carry_i_2_n_0 : STD_LOGIC;
  signal acc10_carry_i_3_n_0 : STD_LOGIC;
  signal acc10_carry_i_4_n_0 : STD_LOGIC;
  signal acc10_carry_n_0 : STD_LOGIC;
  signal acc10_carry_n_1 : STD_LOGIC;
  signal acc10_carry_n_2 : STD_LOGIC;
  signal acc10_carry_n_3 : STD_LOGIC;
  signal acc10_carry_n_4 : STD_LOGIC;
  signal acc10_carry_n_5 : STD_LOGIC;
  signal acc10_carry_n_6 : STD_LOGIC;
  signal acc10_carry_n_7 : STD_LOGIC;
  signal \acc1_reg_n_0_[0]\ : STD_LOGIC;
  signal \acc1_reg_n_0_[10]\ : STD_LOGIC;
  signal \acc1_reg_n_0_[11]\ : STD_LOGIC;
  signal \acc1_reg_n_0_[12]\ : STD_LOGIC;
  signal \acc1_reg_n_0_[13]\ : STD_LOGIC;
  signal \acc1_reg_n_0_[14]\ : STD_LOGIC;
  signal \acc1_reg_n_0_[15]\ : STD_LOGIC;
  signal \acc1_reg_n_0_[16]\ : STD_LOGIC;
  signal \acc1_reg_n_0_[1]\ : STD_LOGIC;
  signal \acc1_reg_n_0_[2]\ : STD_LOGIC;
  signal \acc1_reg_n_0_[3]\ : STD_LOGIC;
  signal \acc1_reg_n_0_[4]\ : STD_LOGIC;
  signal \acc1_reg_n_0_[5]\ : STD_LOGIC;
  signal \acc1_reg_n_0_[6]\ : STD_LOGIC;
  signal \acc1_reg_n_0_[7]\ : STD_LOGIC;
  signal \acc1_reg_n_0_[8]\ : STD_LOGIC;
  signal \acc1_reg_n_0_[9]\ : STD_LOGIC;
  signal data_in_sync1 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal data_in_sync2 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal p_0_in : STD_LOGIC;
  signal quant : STD_LOGIC;
  signal quant_inv_i_1_n_0 : STD_LOGIC;
  signal \NLW_acc10_carry__3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_acc10_carry__3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  attribute ADDER_THRESHOLD : integer;
  attribute ADDER_THRESHOLD of acc10_carry : label is 35;
  attribute ADDER_THRESHOLD of \acc10_carry__0\ : label is 35;
  attribute ADDER_THRESHOLD of \acc10_carry__1\ : label is 35;
  attribute ADDER_THRESHOLD of \acc10_carry__2\ : label is 35;
  attribute ADDER_THRESHOLD of \acc10_carry__3\ : label is 35;
  attribute inverted : string;
  attribute inverted of quant_reg_inv : label is "yes";
begin
acc10_carry: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => acc10_carry_n_0,
      CO(2) => acc10_carry_n_1,
      CO(1) => acc10_carry_n_2,
      CO(0) => acc10_carry_n_3,
      CYINIT => '0',
      DI(3 downto 0) => data_in_sync2(3 downto 0),
      O(3) => acc10_carry_n_4,
      O(2) => acc10_carry_n_5,
      O(1) => acc10_carry_n_6,
      O(0) => acc10_carry_n_7,
      S(3) => acc10_carry_i_1_n_0,
      S(2) => acc10_carry_i_2_n_0,
      S(1) => acc10_carry_i_3_n_0,
      S(0) => acc10_carry_i_4_n_0
    );
\acc10_carry__0\: unisim.vcomponents.CARRY4
     port map (
      CI => acc10_carry_n_0,
      CO(3) => \acc10_carry__0_n_0\,
      CO(2) => \acc10_carry__0_n_1\,
      CO(1) => \acc10_carry__0_n_2\,
      CO(0) => \acc10_carry__0_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => data_in_sync2(7 downto 4),
      O(3) => \acc10_carry__0_n_4\,
      O(2) => \acc10_carry__0_n_5\,
      O(1) => \acc10_carry__0_n_6\,
      O(0) => \acc10_carry__0_n_7\,
      S(3) => \acc10_carry__0_i_1_n_0\,
      S(2) => \acc10_carry__0_i_2_n_0\,
      S(1) => \acc10_carry__0_i_3_n_0\,
      S(0) => \acc10_carry__0_i_4_n_0\
    );
\acc10_carry__0_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => data_in_sync2(7),
      I1 => \acc1_reg_n_0_[7]\,
      O => \acc10_carry__0_i_1_n_0\
    );
\acc10_carry__0_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => data_in_sync2(6),
      I1 => \acc1_reg_n_0_[6]\,
      O => \acc10_carry__0_i_2_n_0\
    );
\acc10_carry__0_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => data_in_sync2(5),
      I1 => \acc1_reg_n_0_[5]\,
      O => \acc10_carry__0_i_3_n_0\
    );
\acc10_carry__0_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => data_in_sync2(4),
      I1 => \acc1_reg_n_0_[4]\,
      O => \acc10_carry__0_i_4_n_0\
    );
\acc10_carry__1\: unisim.vcomponents.CARRY4
     port map (
      CI => \acc10_carry__0_n_0\,
      CO(3) => \acc10_carry__1_n_0\,
      CO(2) => \acc10_carry__1_n_1\,
      CO(1) => \acc10_carry__1_n_2\,
      CO(0) => \acc10_carry__1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => data_in_sync2(11 downto 8),
      O(3) => \acc10_carry__1_n_4\,
      O(2) => \acc10_carry__1_n_5\,
      O(1) => \acc10_carry__1_n_6\,
      O(0) => \acc10_carry__1_n_7\,
      S(3) => \acc10_carry__1_i_1_n_0\,
      S(2) => \acc10_carry__1_i_2_n_0\,
      S(1) => \acc10_carry__1_i_3_n_0\,
      S(0) => \acc10_carry__1_i_4_n_0\
    );
\acc10_carry__1_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => data_in_sync2(11),
      I1 => \acc1_reg_n_0_[11]\,
      O => \acc10_carry__1_i_1_n_0\
    );
\acc10_carry__1_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => data_in_sync2(10),
      I1 => \acc1_reg_n_0_[10]\,
      O => \acc10_carry__1_i_2_n_0\
    );
\acc10_carry__1_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => data_in_sync2(9),
      I1 => \acc1_reg_n_0_[9]\,
      O => \acc10_carry__1_i_3_n_0\
    );
\acc10_carry__1_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => data_in_sync2(8),
      I1 => \acc1_reg_n_0_[8]\,
      O => \acc10_carry__1_i_4_n_0\
    );
\acc10_carry__2\: unisim.vcomponents.CARRY4
     port map (
      CI => \acc10_carry__1_n_0\,
      CO(3) => \acc10_carry__2_n_0\,
      CO(2) => \acc10_carry__2_n_1\,
      CO(1) => \acc10_carry__2_n_2\,
      CO(0) => \acc10_carry__2_n_3\,
      CYINIT => '0',
      DI(3) => \acc1_reg_n_0_[15]\,
      DI(2 downto 0) => data_in_sync2(14 downto 12),
      O(3) => \acc10_carry__2_n_4\,
      O(2) => \acc10_carry__2_n_5\,
      O(1) => \acc10_carry__2_n_6\,
      O(0) => \acc10_carry__2_n_7\,
      S(3) => \acc10_carry__2_i_1_n_0\,
      S(2) => \acc10_carry__2_i_2_n_0\,
      S(1) => \acc10_carry__2_i_3_n_0\,
      S(0) => \acc10_carry__2_i_4_n_0\
    );
\acc10_carry__2_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \acc1_reg_n_0_[15]\,
      I1 => data_in_sync2(15),
      O => \acc10_carry__2_i_1_n_0\
    );
\acc10_carry__2_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => data_in_sync2(14),
      I1 => \acc1_reg_n_0_[14]\,
      O => \acc10_carry__2_i_2_n_0\
    );
\acc10_carry__2_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => data_in_sync2(13),
      I1 => \acc1_reg_n_0_[13]\,
      O => \acc10_carry__2_i_3_n_0\
    );
\acc10_carry__2_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => data_in_sync2(12),
      I1 => \acc1_reg_n_0_[12]\,
      O => \acc10_carry__2_i_4_n_0\
    );
\acc10_carry__3\: unisim.vcomponents.CARRY4
     port map (
      CI => \acc10_carry__2_n_0\,
      CO(3 downto 1) => \NLW_acc10_carry__3_CO_UNCONNECTED\(3 downto 1),
      CO(0) => \acc10_carry__3_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => B"000",
      DI(0) => p_0_in,
      O(3 downto 2) => \NLW_acc10_carry__3_O_UNCONNECTED\(3 downto 2),
      O(1) => \acc10_carry__3_n_6\,
      O(0) => \acc10_carry__3_n_7\,
      S(3 downto 2) => B"00",
      S(1) => \acc10_carry__3_i_1_n_0\,
      S(0) => \acc10_carry__3_i_2_n_0\
    );
\acc10_carry__3_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \acc1_reg_n_0_[16]\,
      I1 => p_0_in,
      O => \acc10_carry__3_i_1_n_0\
    );
\acc10_carry__3_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \acc1_reg_n_0_[16]\,
      I1 => p_0_in,
      O => \acc10_carry__3_i_2_n_0\
    );
acc10_carry_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => data_in_sync2(3),
      I1 => \acc1_reg_n_0_[3]\,
      O => acc10_carry_i_1_n_0
    );
acc10_carry_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => data_in_sync2(2),
      I1 => \acc1_reg_n_0_[2]\,
      O => acc10_carry_i_2_n_0
    );
acc10_carry_i_3: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => data_in_sync2(1),
      I1 => \acc1_reg_n_0_[1]\,
      O => acc10_carry_i_3_n_0
    );
acc10_carry_i_4: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => data_in_sync2(0),
      I1 => \acc1_reg_n_0_[0]\,
      O => acc10_carry_i_4_n_0
    );
\acc1_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => acc10_carry_n_7,
      Q => \acc1_reg_n_0_[0]\,
      R => reset
    );
\acc1_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \acc10_carry__1_n_5\,
      Q => \acc1_reg_n_0_[10]\,
      R => reset
    );
\acc1_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \acc10_carry__1_n_4\,
      Q => \acc1_reg_n_0_[11]\,
      R => reset
    );
\acc1_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \acc10_carry__2_n_7\,
      Q => \acc1_reg_n_0_[12]\,
      R => reset
    );
\acc1_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \acc10_carry__2_n_6\,
      Q => \acc1_reg_n_0_[13]\,
      R => reset
    );
\acc1_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \acc10_carry__2_n_5\,
      Q => \acc1_reg_n_0_[14]\,
      R => reset
    );
\acc1_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \acc10_carry__2_n_4\,
      Q => \acc1_reg_n_0_[15]\,
      R => reset
    );
\acc1_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \acc10_carry__3_n_7\,
      Q => \acc1_reg_n_0_[16]\,
      R => reset
    );
\acc1_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \acc10_carry__3_n_6\,
      Q => p_0_in,
      R => reset
    );
\acc1_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => acc10_carry_n_6,
      Q => \acc1_reg_n_0_[1]\,
      R => reset
    );
\acc1_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => acc10_carry_n_5,
      Q => \acc1_reg_n_0_[2]\,
      R => reset
    );
\acc1_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => acc10_carry_n_4,
      Q => \acc1_reg_n_0_[3]\,
      R => reset
    );
\acc1_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \acc10_carry__0_n_7\,
      Q => \acc1_reg_n_0_[4]\,
      R => reset
    );
\acc1_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \acc10_carry__0_n_6\,
      Q => \acc1_reg_n_0_[5]\,
      R => reset
    );
\acc1_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \acc10_carry__0_n_5\,
      Q => \acc1_reg_n_0_[6]\,
      R => reset
    );
\acc1_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \acc10_carry__0_n_4\,
      Q => \acc1_reg_n_0_[7]\,
      R => reset
    );
\acc1_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \acc10_carry__1_n_7\,
      Q => \acc1_reg_n_0_[8]\,
      R => reset
    );
\acc1_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \acc10_carry__1_n_6\,
      Q => \acc1_reg_n_0_[9]\,
      R => reset
    );
\data_in_sync1_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => data_in(0),
      Q => data_in_sync1(0),
      R => reset
    );
\data_in_sync1_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => data_in(10),
      Q => data_in_sync1(10),
      R => reset
    );
\data_in_sync1_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => data_in(11),
      Q => data_in_sync1(11),
      R => reset
    );
\data_in_sync1_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => data_in(12),
      Q => data_in_sync1(12),
      R => reset
    );
\data_in_sync1_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => data_in(13),
      Q => data_in_sync1(13),
      R => reset
    );
\data_in_sync1_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => data_in(14),
      Q => data_in_sync1(14),
      R => reset
    );
\data_in_sync1_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => data_in(15),
      Q => data_in_sync1(15),
      R => reset
    );
\data_in_sync1_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => data_in(1),
      Q => data_in_sync1(1),
      R => reset
    );
\data_in_sync1_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => data_in(2),
      Q => data_in_sync1(2),
      R => reset
    );
\data_in_sync1_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => data_in(3),
      Q => data_in_sync1(3),
      R => reset
    );
\data_in_sync1_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => data_in(4),
      Q => data_in_sync1(4),
      R => reset
    );
\data_in_sync1_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => data_in(5),
      Q => data_in_sync1(5),
      R => reset
    );
\data_in_sync1_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => data_in(6),
      Q => data_in_sync1(6),
      R => reset
    );
\data_in_sync1_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => data_in(7),
      Q => data_in_sync1(7),
      R => reset
    );
\data_in_sync1_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => data_in(8),
      Q => data_in_sync1(8),
      R => reset
    );
\data_in_sync1_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => data_in(9),
      Q => data_in_sync1(9),
      R => reset
    );
\data_in_sync2_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => data_in_sync1(0),
      Q => data_in_sync2(0),
      R => reset
    );
\data_in_sync2_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => data_in_sync1(10),
      Q => data_in_sync2(10),
      R => reset
    );
\data_in_sync2_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => data_in_sync1(11),
      Q => data_in_sync2(11),
      R => reset
    );
\data_in_sync2_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => data_in_sync1(12),
      Q => data_in_sync2(12),
      R => reset
    );
\data_in_sync2_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => data_in_sync1(13),
      Q => data_in_sync2(13),
      R => reset
    );
\data_in_sync2_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => data_in_sync1(14),
      Q => data_in_sync2(14),
      R => reset
    );
\data_in_sync2_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => data_in_sync1(15),
      Q => data_in_sync2(15),
      R => reset
    );
\data_in_sync2_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => data_in_sync1(1),
      Q => data_in_sync2(1),
      R => reset
    );
\data_in_sync2_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => data_in_sync1(2),
      Q => data_in_sync2(2),
      R => reset
    );
\data_in_sync2_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => data_in_sync1(3),
      Q => data_in_sync2(3),
      R => reset
    );
\data_in_sync2_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => data_in_sync1(4),
      Q => data_in_sync2(4),
      R => reset
    );
\data_in_sync2_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => data_in_sync1(5),
      Q => data_in_sync2(5),
      R => reset
    );
\data_in_sync2_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => data_in_sync1(6),
      Q => data_in_sync2(6),
      R => reset
    );
\data_in_sync2_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => data_in_sync1(7),
      Q => data_in_sync2(7),
      R => reset
    );
\data_in_sync2_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => data_in_sync1(8),
      Q => data_in_sync2(8),
      R => reset
    );
\data_in_sync2_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => data_in_sync1(9),
      Q => data_in_sync2(9),
      R => reset
    );
pdm_out_reg: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => quant,
      Q => pdm_out,
      R => reset
    );
quant_inv_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => p_0_in,
      I1 => reset,
      O => quant_inv_i_1_n_0
    );
quant_reg_inv: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => clk,
      CE => '1',
      D => quant_inv_i_1_n_0,
      Q => quant,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity FNPLL_DS_dac_0_0 is
  port (
    clk : in STD_LOGIC;
    reset : in STD_LOGIC;
    data_in : in STD_LOGIC_VECTOR ( 15 downto 0 );
    pdm_out : out STD_LOGIC
  );
  attribute NotValidForBitStream : boolean;
  attribute NotValidForBitStream of FNPLL_DS_dac_0_0 : entity is true;
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of FNPLL_DS_dac_0_0 : entity is "FNPLL_DS_dac_0_0,DS_dac,{}";
  attribute downgradeipidentifiedwarnings : string;
  attribute downgradeipidentifiedwarnings of FNPLL_DS_dac_0_0 : entity is "yes";
  attribute ip_definition_source : string;
  attribute ip_definition_source of FNPLL_DS_dac_0_0 : entity is "module_ref";
  attribute x_core_info : string;
  attribute x_core_info of FNPLL_DS_dac_0_0 : entity is "DS_dac,Vivado 2025.1";
end FNPLL_DS_dac_0_0;

architecture STRUCTURE of FNPLL_DS_dac_0_0 is
  attribute x_interface_info : string;
  attribute x_interface_info of clk : signal is "xilinx.com:signal:clock:1.0 clk CLK";
  attribute x_interface_mode : string;
  attribute x_interface_mode of clk : signal is "slave clk";
  attribute x_interface_parameter : string;
  attribute x_interface_parameter of clk : signal is "XIL_INTERFACENAME clk, ASSOCIATED_RESET reset, FREQ_HZ 10000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, INSERT_VIP 0";
  attribute x_interface_info of reset : signal is "xilinx.com:signal:reset:1.0 reset RST";
  attribute x_interface_mode of reset : signal is "slave reset";
  attribute x_interface_parameter of reset : signal is "XIL_INTERFACENAME reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
begin
U0: entity work.FNPLL_DS_dac_0_0_DS_dac
     port map (
      clk => clk,
      data_in(15 downto 0) => data_in(15 downto 0),
      pdm_out => pdm_out,
      reset => reset
    );
end STRUCTURE;
